\t (00:00:01) allegro 16.3 S021 (v16-3-85BG) i86
\t (00:00:01) 

\t (00:00:03) Starting new drawing...
\i (00:00:03) trapsize 468
\i (00:00:03) trapsize 462
\i (00:00:03) trapsize 459
\i (00:00:03) trapsize 656
\i (00:00:04) generaledit 
\i (00:00:53) open 
\i (00:01:16) fillin "J:\PCB_Layout\Layout_Libraries\LIBRARIES\SYMBOLS_2009\TO_220_VERT.dra"
\i (00:01:16) cd "J:\PCB_Layout\Layout_Libraries\LIBRARIES\SYMBOLS_2009"
\t (00:01:16) Opening existing drawing...
\i (00:01:17) trapsize 207
\d (00:01:17) Database opened: J:/PCB_Layout/Layout_Libraries/LIBRARIES/SYMBOLS_2009/TO_220_VERT.dra
\i (00:01:17) generaledit 
\i (00:01:50) show measure 
\i (00:01:51) pick grid -1.68 122.21
\t (00:01:51) last pick:  0.00  125.00
\i (00:01:51) pick grid -12.84 -27.34
\t (00:01:51) last pick:  -25.00  -25.00
\i (00:07:05) replace padstack 
\i (00:07:06) pick grid 18.56 109.82
\t (00:07:06) last pick:  0.00  100.00
\i (00:07:07) setwindow form.mini
\i (00:07:07) FORM mini newname_browse  
\f (00:07:07) Select a padstack:
\i (00:07:31) fillin "S45h77"
\i (00:07:38) FORM mini replace  
\i (00:07:39) setwindow pcb
\i (00:07:39) pick grid 18.97 -28.58
\t (00:07:39) last pick:  0.00  0.00
\i (00:07:44) setwindow form.mini
\i (00:07:44) FORM mini newname C45H77 
\i (00:07:46) FORM mini replace  
\i (00:07:46) setwindow pcb
\i (00:07:46) prepopup 228.01 32.98
\i (00:07:47) done 
\t (00:07:47) Performing DRC...
\t (00:07:47) No DRC errors detected.
\i (00:07:47) generaledit 
\i (00:20:08) save 
\f (00:20:08) J:/PCB_Layout/Layout_Libraries/LIBRARIES/SYMBOLS_2009/TO_220_VERT.dra: File Exists. Overwrite? 
\i (00:20:08) fillin yes 
\t (00:20:09) Symbol 'to_220_vert.psm' created.
\i (00:20:09) generaledit 
\i (00:21:19) open 
\i (00:21:31) fillin "J:\PCB_Layout\Layout_Libraries\LIBRARIES\Orcad_LAYOUT_libs\allegro\lcon100t_llb.brd"
\i (00:21:31) cd "J:\PCB_Layout\Layout_Libraries\LIBRARIES\Orcad_LAYOUT_libs\allegro"
\t (00:21:31) Opening existing drawing...
\w (00:21:31) WARNING(SPMHDB-214): Allegro PCB Design L opening an Allegro XL design.
\w (00:21:31) WARNING(SPMHDB-213): DRC set to "out of date". This product supports a different DRC set than last product used on drawing.
\w (00:21:31) WARNING(SPMHOD-33): Database was last saved by a higher tier tool ... Allegro XL. There may be constraints, rules and other design data that may be ignored in this tool.
\i (00:21:36) fillin confirm
\i (00:21:37) trapsize 802
\i (00:21:37) trapsize 789
\i (00:21:37) trapsize 1038
\d (00:21:37) Database opened: J:/PCB_Layout/Layout_Libraries/LIBRARIES/Orcad_LAYOUT_libs/allegro/lcon100t_llb.brd
\i (00:21:37) generaledit 
\i (00:22:06) zoom in 1 
\i (00:22:06) setwindow pcb
\i (00:22:06) zoom in 7137.5 11185.5
\i (00:22:06) trapsize 519
\i (00:22:06) zoom in 1 
\i (00:22:06) setwindow pcb
\i (00:22:06) zoom in 7179.1 11268.6
\i (00:22:06) trapsize 260
\i (00:22:06) zoom in 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom in 7184.3 11279.0
\i (00:22:07) trapsize 130
\i (00:22:07) zoom in 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom in 7192.1 11297.2
\i (00:22:07) trapsize 65
\i (00:22:07) zoom in 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom in 7194.7 11306.3
\i (00:22:07) trapsize 32
\i (00:22:07) zoom out 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom out 7194.7 11307.0
\i (00:22:07) trapsize 65
\i (00:22:07) zoom out 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom out 7194.7 11307.0
\i (00:22:07) trapsize 130
\i (00:22:07) zoom out 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom out 7194.8 11307.0
\i (00:22:07) trapsize 260
\i (00:22:07) zoom out 1 
\i (00:22:07) setwindow pcb
\i (00:22:07) zoom out 7194.8 11306.9
\i (00:22:07) trapsize 519
\i (00:22:08) zoom out 1 
\i (00:22:08) setwindow pcb
\i (00:22:08) zoom out 7194.8 11307.0
\i (00:22:08) trapsize 1038
\i (00:22:08) zoom out 1 
\i (00:22:08) setwindow pcb
\i (00:22:08) zoom out 7345.1 11704.6
\i (00:22:08) trapsize 1038
\i (00:22:08) zoom out 1 
\i (00:22:08) setwindow pcb
\i (00:22:08) zoom out 7345.1 11704.6
\i (00:22:08) trapsize 1038
\i (00:22:18) zoom in 1 
\i (00:22:18) setwindow pcb
\i (00:22:18) zoom in 6576.9 10313.6
\i (00:22:18) trapsize 519
\i (00:22:28) zoom in 1 
\i (00:22:28) setwindow pcb
\i (00:22:28) zoom in 12732.5 12119.8
\i (00:22:28) trapsize 260
\i (00:22:28) zoom in 1 
\i (00:22:28) setwindow pcb
\i (00:22:28) zoom in 12732.5 12119.8
\i (00:22:28) trapsize 130
\i (00:22:28) zoom in 1 
\i (00:22:28) setwindow pcb
\i (00:22:28) zoom in 12732.6 12119.8
\i (00:22:28) trapsize 65
\i (00:22:28) zoom in 1 
\i (00:22:28) setwindow pcb
\i (00:22:28) zoom in 12732.6 12119.8
\i (00:22:28) trapsize 32
\i (00:22:33) zoom out 1 
\i (00:22:33) setwindow pcb
\i (00:22:33) zoom out 12151.3 12098.4
\i (00:22:33) trapsize 65
\i (00:22:33) zoom out 1 
\i (00:22:33) setwindow pcb
\i (00:22:33) zoom out 12151.4 12098.4
\i (00:22:33) trapsize 130
\i (00:22:46) zoom out 1 
\i (00:22:46) setwindow pcb
\i (00:22:46) zoom out 12286.3 12360.5
\i (00:22:46) trapsize 260
\i (00:22:46) zoom out 1 
\i (00:22:46) setwindow pcb
\i (00:22:46) zoom out 12281.2 12350.1
\i (00:22:46) trapsize 519
\i (00:22:47) zoom out 1 
\i (00:22:47) setwindow pcb
\i (00:22:47) zoom out 10647.6 12329.4
\i (00:22:47) trapsize 1038
\i (00:23:35) exit