\t (00:00:06) allegro 17.4 S004 Windows SPB 64-bit Edition
\t (00:00:06)     Journal start - Thu May 14 13:22:31 2020
\t (00:00:06)         Host=MICHELANGELO User=jrosal Pid=13524 CPUs=8
\t (00:00:06) CmdLine= C:\Cadence\SPB_17.4\tools\bin\allegro.exe
\t (00:00:06) 
   (00:00:07) Loading axlcore.cxt 
\t (00:00:07) Loading "C:/SPB_Data/cdssetup/OrCAD_Capture/17.4.0/tclscripts/capAutoLoad/EDMClient/EDM/ClientAdapter/Skill/edm.csj"
\t (00:00:07) Log will be written to C:\Users\jrosal\AppData\Local/edm/edmSkill.log
\t (00:00:10) Opening existing design...
\i (00:00:11) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged 10020895rA_BBB1
\d (00:00:11) Design opened: J:/PCB_Layout/Open_Work_Space/10020895-BBB1/allegro/10020895rA_BBB1.brd
\i (00:00:15) trapsize 2471
\i (00:00:15) trapsize 2751
\i (00:00:16) trapsize 1448
\i (00:00:16) trapsize 1448
\i (00:00:18) generaledit 
\i (00:00:44) open 
\i (00:01:11) fillin "X:/707976_EPBuoyPrototypeAndTesting/EE.Drawings/BidirectionalPower/BridgeControl/Rev1/allegro/100221366rB_PB_BridgeControl.brd"
\i (00:01:11) cd "X:/707976_EPBuoyPrototypeAndTesting/EE.Drawings/BidirectionalPower/BridgeControl/Rev1/allegro"
\t (00:01:11) Opening existing design...
\i (00:01:20) fillin yes 
\i (00:01:27) trapsize 9726
\t (00:01:28)     Journal end - Thu May 14 13:23:52 2020