\t (00:10:07) allegro 17.2 S032 Windows SPB 64-bit Edition
\t (00:10:07)     Journal start - Mon Nov 11 07:35:17 2019
\t (00:10:07)         Host=PJ User=jimm Pid=10072 CPUs=8
\t (00:10:07) CmdLine= C:\Cadence\SPB_17.2\tools\bin\allegro.exe
\t (00:10:07) 
\d (00:10:07) Design opened: //atlas.shore.mbari.org/ProjectLibrary/TechServices/PCB_Layout/Open_Work_Space/Durafet interface board/Allegro/Durafet_Interface_Board_JOSE.brd
\i (00:10:07) generaledit 
\i (00:10:13) prmed 
\i (00:10:21) setwindow form.prmedit
\i (00:10:21) FORM prmedit cancel  
\i (00:10:21) setwindow pcb
\i (00:10:21) generaledit 
\i (00:10:25) cmgr 
\i (00:10:25) setwindow cmgr
\i (00:10:25) cm newView ( kConsmgr worksheet 53:Electrical "1:Electrical Constraint Set" 7:Routing 8:Wiring )
\i (00:10:26) cm select ( frame ( kConsmgr workbook 53:Electrical "1:Electrical Constraint Set" 7:Routing ) )
\i (00:10:26) cm select ( frame ( kConsmgr workbook 53:Electrical "1:Electrical Constraint Set" 7:Routing ) )
\i (00:10:26) cm selectDesignTab ( kConsmgr worksheet 53:Electrical "1:Electrical Constraint Set" 7:Routing 8:Wiring ) 0
\i (00:10:26) setwindow pcb
\i (00:10:26) generaledit 
\i (00:10:33) setwindow cmgr
\i (00:10:33) cm newView ( kConsmgr worksheet 53:Electrical 66:Net 25:Routing 26:Wiring )
\i (00:10:33) cm select ( frame ( kConsmgr workbook 53:Electrical 66:Net 25:Routing ) )
\i (00:10:33) cm select ( frame ( kConsmgr workbook 53:Electrical 66:Net 25:Routing ) )
\i (00:10:33) cm expand ( row ( Design "Durafet_Interface_Board_JOSE" ) )
\i (00:10:33) cm selectDesignTab ( kConsmgr worksheet 53:Electrical 66:Net 25:Routing 26:Wiring ) 0
\i (00:10:44) cm select ( frame ( kConsmgr workbook 78:Spacing "79:Spacing Constraint Set" "80:All Layers" ) )
\i (00:10:44) cm select ( frame ( kConsmgr workbook 78:Spacing "79:Spacing Constraint Set" "80:All Layers" ) )
\i (00:10:44) cm select ( frame ( kConsmgr workbook 78:Spacing "79:Spacing Constraint Set" "80:All Layers" ) )
\i (00:10:44) cm expand ( row ( Design "Durafet_Interface_Board_JOSE" ) )
\i (00:10:44) cm selectDesignTab ( kConsmgr worksheet 78:Spacing "79:Spacing Constraint Set" "80:All Layers" "167:All Layers" ) 0
\i (00:11:08) cm close ( frame ( kConsmgr workbook 53:Electrical "1:Electrical Constraint Set" 7:Routing ) )
\i (00:11:08) cm close ( frame ( kConsmgr workbook 53:Electrical 66:Net 25:Routing ) )
\i (00:11:08) cm close ( frame ( kConsmgr workbook 78:Spacing "79:Spacing Constraint Set" "80:All Layers" ) )
\i (00:11:08) cm exit
\i (00:11:18) setwindow pcb
\i (00:11:18) opencd X:/TechServices/PCB_Layout/Open_Work_Space/lowpowerswitch/allegro/lowpowerswitch.brd 
\e (00:11:18) Do you want to save the changes you made to Durafet_Interface_Board_JOSE.brd?
\i (00:11:21) fillin no 
\t (00:11:21) Opening existing design...
\w (00:11:21) WARNING(SPMHDB-212): This design has functionality disabled due to the current product plus options selected. The following features are disabled: Via Z.  [help]
\i (00:11:22) fillin confirm
\i (00:11:22) trapsize 41
\t (00:11:22)     Journal end - Mon Nov 11 07:36:32 2019