\t (00:00:00) allegro 23.1 S007 (4241052) [9/25/2024] Windows SPB 64-bit Edition
\t (00:00:00)     Journal start - Thu Nov 14 11:59:46 2024
\t (00:00:00)         Host=ARCHER2024 User=jrosal Pid=23168 CPUs=32
\t (00:00:00) CmdLine= c:\cadence\spb_23.1\tools\bin\allegro.exe X:\TechServices\PCB_Layout\Open_Work_Space\GenePuck\Release_A\100221480rA_ISFETInterfacePCB.brd
\t (00:00:00) 
\t (00:00:00) Loading axlcore.cxt 
\t (00:00:00) Loading "C:/Users/jrosal/AppData/Roaming/SPB_Data/cdssetup/OrCAD_Capture/tclscripts/capAutoLoad/EDMClient/EDM/ClientAdapter/Skill/edm.csj"
\t (00:00:00) Log will be written to C:\Users\jrosal\AppData\Roaming/edm/edmSkill.log
\t (00:00:05) Opening existing design...
\i (00:00:06) fillin no 
\t (00:00:06) Starting new design...
\i (00:00:07) trapsize 116667
\i (00:00:07) etchedit 
\i (00:00:09) exit 
\t (00:00:09)     Journal end - Thu Nov 14 11:59:54 2024