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(    Dangling Line, Via and Antenna Report                            )
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(    Drawing          : 100221480rB_ISFETInterfacePCB.brd             )
(    Software Version : 23.1S007                                      )
(    Date/Time        : Thu Nov 14 12:12:58 2024                      )
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Report methodology:
  - Dangling lines have at least one end not connected.
  - Dangling vias have one or no connection
      - Plus are not a test, thieving or netshort property via.
  - Antenna vias do not have connections on their start and end layers.
      - Plus they are not a thieving vias.
      - Optionally, VOLTAGE nets, testvias and through vias can be suppressed with
        the environment variable report_antennavia.
      - Section may be suppressed by variable report_noantennavia.
  - Not part of the current partition.
  - To suppress items in dangle report add the OK_DANGLE property to the via
    or connect line.

<< Dangling Lines >>  - Location marked with a star (*) is dangling.
  Net                 Layer                  Length       Location
  ------------------------------------------------------------------------------------------
  Dummy Net            TOP                   0.0818      (0.0360 0.0210) to *(0.0800 0.0900)
  Dummy Net            TOP                   0.0864      (0.0000 0.0560) to *(-0.0795 0.0899)
  Dummy Net            TOP                   0.1073      (-0.0360 0.0210) to *(-0.1015 -0.0640)

<< Summary >>
  Total dangling lines:       3
  Total dangling vias:        0
  Total antenna vias:         0
