Index of /internal/projects/TechServices/PCB_Layout/Open_Work_Space/PB_cellbypass/Allegro

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[DIR]LOG/2017-04-07 12:59 -  
[DIR]Manufacturing/2017-04-07 12:52 -  
[   ]PB_cellBypass.brd2017-04-07 14:01 329K 
[   ]allegro.jrl2022-06-21 08:49 3.0K 
[   ]devices.dml2017-04-07 11:18 43  
[TXT]eco.txt2017-04-07 10:42 3.6K 
[   ]eco.txt,12017-04-07 10:35 19K 
[TXT]master.tag2017-04-07 14:01 19  
[TXT]nc_param.txt2017-04-07 11:16 394  
[   ]netlist.log2017-04-07 10:42 2.3K 
[   ]pstchip.dat2017-04-07 10:42 5.0K 
[   ]pstchip.dat,12017-04-07 10:34 5.0K 
[   ]pstxnet.dat2017-04-07 10:42 5.0K 
[   ]pstxnet.dat,12017-04-07 10:34 5.0K 
[   ]pstxprt.dat2017-04-07 10:42 6.1K 
[   ]pstxprt.dat,12017-04-07 10:34 6.1K 
[TXT]pxlBA.txt2017-04-07 10:42 3.5K 
[DIR]signoise.run/2017-04-07 10:52 -  

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