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{\Large \bf 
The IBC High-Power Switch} \\[0.5cm] 
M.B. Matthews \\
Version 1.1, Sept. 21, 1992
\ec

\section{Introduction}
This document describes the design of the MBARI IBC High-Power Switch (HPS).
The HPS is designed to make and break repeatedly a current of 
25A on the 240VDC high-power bus without relay arcing
or other pathological phenomena that limit the lifetime of the relay.

The method we have chosen consists of a double-pole relay
in parallel with a pair of high-power IGBT's Q7 and Q8.
The basic operation of the switch is described as follows:
Upon receipt of an ON command from the system, 
the switch-closing sequence is initiated
by turning IGBT Q8 fully on and turning IGBT Q7 partially on such that
the current in these devices reaches a small preset value. 
This low-current charging phase prevents
the IGBT's from experiencing a high-current condition 
from either a dead short or a large capacitive load.
After the low-current phase, Q7 is turned fully on. 
If both collector-emitter potentials across Q7 and Q8 fall
below approximately 4 volts, the relay is turned on.
The IGBT's remain on during the entire time that the relays are on.
If either a overcurrent condition (> 30A) or an overtemperature condition
(> 125 degrees C) is experienced or
if the OFF command is received, the HPS is reset and
the relay will open immediately.
The IGBT's remain on for a short period of time after the relay opens
and then turn off. A reset event initiates an interrupt to the system.
In the event of a catastrophic failure of the system, a 30A fuse will open.

The system can monitor the switch current in the range 
(--25,+25A) by means of a 12-bit digitized
voltage measurement across 5m$\Omega$ shunt resistor R38.
This measurement is accurate to 1\% of full scale or $\pm 25$mA
within a bandwidth of 100Hz.

\section{Physical Characteristics}
The HPS board requires one 6-inch IBC backplane slot.
The tallest component on the board is 1.2 inches.
The IGBT's will require an undetermined amount of convection cooling
as a function of switching rate.

\section{Power Requirements}
The worst-case input power requirement from the IBC backplane is +5VDC
approximately 600mA. 
The individual component current requirements are given in Table \ref{power}.
%
\begin{table}[hbt]
\begin{center}
\begin{tabular}{ll}
{\em component} & {\em current} \\ \hline
EP910 EPLD 	& 80mA	\\
MAX164		& 6mA	\\
74HC640		& 67mA	\\
HPR105 (U15)	& 50mA	\\
HPR105 (U16)	& 100mA	\\
HPR105 (U17)	& 10mA	\\
2 HCPL-2231 optoisolators & 34mA \\
3 4N33 optoisolators & 6mA \\
relay coil	& 210mA \\
\hline
total 		& 563mA \\
\end{tabular}
\end{center}
\label{power}
\end{table}
%
The HPS power system consists of three separate isolated $\pm 15$V
power busses labelled ($\pm$Vi,GNDi), for $i=1,2,3$,
supplied by power modules U16, U17, and U15, respectively.
The ($\pm$V1, GND1) regulated power bus is common to the load side of the
high-side relay contacts (recall that the relay is a double pole device with
the load connected between high-side and low-side contacts).
It supplies power for the IR2121 Gate Driver for IGBT Q6
as well as the current sense amplifiers U10 and the isolation amplifier U1.
The ($\pm$V2, GND2) unregulated power bus is common to the power side of the 
low-side relay contacts. It supplies the gate drive for IGBT Q7
as well as the voltage for the collector-emitter sense circuit for Q7.
The ($\pm$V3, GND3) regulated power bus is common to the 
IBC common and provides
power to both isolation amplifier U1 and the A/D-converter U2.

\section{IBC Interface}
The HPS board is decoded by the EP900 EPLD U8 at individual
word-wide 
I/O addresses 70-7F selectable by jumper JP4 as shown in Table \ref{t1}.
%
\begin{figure}[hbt]
\begin{center}
\begin{tabular}{|c|l|l|l|} \hline
{\em address} & \multicolumn{3}{c|}{\em jumpers} \\ \hline
70-71	& JP3-1,2 & JP3-3,4 & JP3-5,6 \\
72-73	&         & JP3-3,4 & JP3-5,6 \\
74-75	& JP3-1,2 &         & JP3-5,6 \\
76-77	&         &         & JP3-5,6 \\
78-79	& JP3-1,2 & JP3-3,4 &         \\
7A-7B	&         & JP3-3,4 &         \\
7C-7D	& JP3-1,2 &         &         \\
7E-7F	&         & none    &         \\
\hline
\end{tabular}
\end{center}
\label{t1}
\end{figure}
%
The {\tt BRDSEL} output of U8 goes high when the selected address is present
on the IBC address bus.
The EPLD has a 3-bit command/status register corresponding to bits D0-D2 on 
the IBC data bus. The function of these two registers is shown in 
Table \ref{t2}.
%
\begin{figure}[hbt]
\begin{center}
\begin{tabular}{|c|l|l|} \hline
{\em bit} & {\em command} & {\em status} \\ \hline
0	& -	 & {\tt RELAY} -- relay on \\
1	& {\tt ADCSEL} -- ADC select & {\tt ADCRDY} -- ADC conversion complete \\
2	& {\tt ON} -- on/off command	 & {\tt ON} -- on/off status \\
\hline
\end{tabular}
\end{center}
\label{t2}
\end{figure}
%
During a write to the HPS, i.e., on the rising edge of
{\tt IOWR*} with {\tt BRDSEL} high, data bits D0-D2 are latched into the
command register. When Bit 1 ({\tt ADCSEL}) of the command register is high,
the A/D-converter is selected for reading; when {\tt ADCSEL} is low,
the status register is selected for reading.
All write operations to the HPS will go to the command register.
The operation of the A/D-converter is discussed in Section \ref{adc}. 
Bit 2 ({\tt ON}) of the command register controls the on/off function of the 
high-power switch.
When {\tt ON} is set, the closing sequence of the switch is initiated.
Resetting {\tt ON} initiates the switch opening sequence.
An overcurrent event {\tt OC}, an overtemperature event {\tt OT},
or an error event {\tt ERROR} also resets {\tt ON}.
The opening and closing sequences are described in detail in Section \ref{sw}.

\section{Current Sensing}
The current sense signal {\tt ISENSE} is filtered version of
the voltage drop across the 5m$\Omega$ shunt resistor R38;
the scale of {\tt ISENSE} is approximately 210mV/A;
the filter is a 2-pole low-pass filter with poles at 100Hz and 250Hz. 
The {\tt ISENSE} signal is used for both current measurements
and overcurrent detection. 
It is passed to the nonisolated side of the HPS,
i.e., the side with the IBC common, by means of isolation amplifier U1,
and is subsequently digitized by the Maxim MAX164 A/D-converter.

\section{Overcurrent and Overtemperature Detection}
The overcurrent detector asserts an overcurrent event {\tt OC} signal
when the current sense signal {\tt ISENSE} exceeds the equivalent of 30A. 
The overtemperature detector asserts an overtemperature event {\tt OT}
when the temperature of the AD592 temperature sensor U14 mounted on the
IGBT heatsink exceeds a value set by the sense resistor R33 
and the trip level of the Schmitt trigger U3A.
The value of R33 should be determined during calibration; a suggested 
temperature threshold is 125 degrees C.

\section{Reset Interrupt}
\label{int}
The EPLD generates a system interrupt {\tt INT}
when the {\tt ON} bit is reset by either an overcurrent event, 
an overtemperature event or an error event.
Interrupt {\tt INT} is always enabled;
it is cleared by a write to the HPS.
Header JP1 connects the interrupt to any one of the eight
interrupt line on the IBC backplane.

\section{A/D-Converter Operation}
\label{adc}
The Maxim MAX164 A/D-converter (ADC)
U7 is a 12-bit, 8$\mu$S device which provides
for both word-wide and byte-wide data reading. We use this device in its
two-byte read ROM mode; the suggested conversion and reading sequence for this
mode is as follows:
%
\benum
\item	Set {\tt ADCSEL} in the command register to select the ADC for reading;
\item	Perform a dummy read of the ADC to start a conversion.
	The {\tt ADCRDY} status bit will indicate that the conversion is
	complete.
\item	Read the high byte of the ADC; the lower four bits correspond to 
	data bits DB11-DB8. The {\tt ADCRDY} is reset on this read.
\item	Read the low byte of the ADC. This byte corresponds to data bits D0-D7.
	A second conversion is started when the low byte is read;
	the subsequent data may be read at the end of conversion, or it
	may be ignored.
\eenum
%
The 12-bit data from the A/D-converter correspond to a current range of
(-25,+25A); this corresponds to a resolution of approximately 11.6mA/bit.

\section{Switch Opening and Closing Sequence}
\label{sw}
The high-power switch closing sequence is initiated by either
setting the {\tt ON} bit high in the command register or pushing the
override pushbutton S1; this causes the {\tt ON} output of U8 to go high.
Initially, with {\tt ON} low, the optocouplers U5 and U7 are off and on,
respectively; Q3 shorts the {\tt ERR} line to ground and Q4 is off causing
U10B to have a gain of 41 corresponding to a current measurement of
approximately 200mV/A from the current shunt R38.
When {\tt ON} goes high,
the output of the "turn-off delay" goes immediately high 
providing a 15V high logic signal to the {\tt IN} control of the
IR2121 driver chip; simultaneously, the low-side IGBT Q7 is turned full on.
The operation of the IR2121 is such that, upon receipt of an active signal 
at {\tt IN}, {\tt OUT} provides a full 15V gate drive to IGBT Q6.
If the sense voltage at {\tt CS} exceeds a nominal value of 230mV
corresponding to a sensed current of approximately 1A,
the IR2121 switches to a linear mode in which the gate drive to IGBT Q6 is
controlled to keep {\tt CS} at 230mV.
This low-level current is maintained for approximately 100mS until
the "high-current turn-on delay" U3D goes low and turns Q3 and Q4 off and
on, respectively. 
With Q4 conducting, the gain of U10B changes to 
unity causing the gate drive control to limit IGBT Q6 to approximately 45A.
If this high-current condition persists for more than approximately
20uS (i.e., the time it takes C9 to charge to 1.8V at 100uA), 
the {\tt OUT} gate drive is turned off 
and {\tt ERR} asserts the error signal ERROR which
causes the {\tt ON} bit to be reset in the EPLD.
Alternatively, if no high-current condition results after the
turn-on delay, IGBT Q6 is turned full on.

During the turn-on sequence, when the collector-emitter voltage across
both IGBTs Q7 and Q6 falls below approximately 4V, signals P1 and P2 go high.
If P1, P2 and {\tt ON} are high and no overtemperature or overcurrent
condition exist, i.e., {\tt OT}, {\tt OC}, and {\tt ERROR} are low,
{\tt RELAY} goes high and turns on the relay.
{\tt RELAY} is also available as Bit 0 in the status register.

The overcurrent detector U9 asserts an {\tt OC} signal if and only if 
the sensed current exceeds approximately 30A. 
The {\tt OC} overcurrent condition resets the {\tt ON} bit.
Similarly, if the IGBT heatsink temperature exceeds approximately
150 degrees C, the {\tt OT} signal is asserted resetting {\tt ON}.

If at any time the {\tt ON} bit is reset, either by a write command from
the system CPU or by an error condition ({\tt OC}, {\tt OT}, or {\tt ERROR}),
{\tt RELAY} goes low immediately and the relay is opened.
The IGBTs remain conducting for approximately 50mS
until the ``turn-off delay'' U3C goes low and turns off the IR2121 U6.
This delay is to prevent arcing in
the relay contacts when opened under full current.
Note also that {\tt ON} being low does not necessarily mean that the
relay is open; both {\tt ON} and {\tt RELAY} low is sufficient indication.

\section{Calibration}
The current sense amplifier U10B is calibrated by selecting R5 such that
the {\tt CS} threshold corresponds to approximately 1A.
This can be done as follows: (1) disconnect jumper JP4;
(2) short U3D pin 13 to common; (3) connect a voltage source to
the {\tt CS} input of U6 and increase the voltage until {\tt out} goes low.
Use this threshold voltage $V_{cs}$ to select R5 such that 
$R5 = 0.005 \times 82,500 \times i_{cs} / V_{cs}$, where $i_{cs}$ is the
required quiescent current.
The current sense isolation amplifier U1 is calibrated by shorting
R38 and adjusting offset adjust R45 for a 0x800 reading from the ADC.
The current sense gain is calibrated
by connecting a 125mV source across R38 and
adjusting R44 for a 0xfff reading from the ADC.
The overtemperature detector is calibrated by connecting a voltage source
to U3 pin 1 and measuring the voltage at which U3 pin 3 goes high.
R33 should then be selected such that 
$\mbox{R33} = V_T \times (298.2 + T - 25)^{-1} \times 10^6$,
where $V_T$ is the trigger threshold of U3 and $T$ is the threshold 
temperature in degrees C.
 

\newpage

\section{High-Power Switch Board Configuration Template}

\bigskip
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Date:\\

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Application:\\

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Revision:\\

\bigskip
\bigskip
\nin
Address Selection (JP3):\\

\bigskip
\nin
Interrupt Selection (JP1):\\

\bigskip
\nin
Calibration Notes:

\end{document}
