A+PLUS Design Processor Utilization Report                           ibc196.rpt 
@(#) FIT Version 7.0    6/26/90 23:37:17 47.1
 ***** Design implemented successfully 
 
Ed Mellinger
MBARI
10 December 91
MBARI 4006
no rev
EP630
IBC-196 Decode and Waitstate EPLD

%**********************************************************%

Input files : ibc196.adf 
ADP Options: Minimization = Yes,  Inversion Control = No,  LEF Analysis = Yes

OPTIONS: TURBO = ON, SECURITY = OFF

               EP630 
             - - - - -
       Gnd -|1      24|- Vcc 
       A15 -|2      23|- A14 
       A12 -|3      22|- /RAM 
       A13 -|4      21|- /ROM 
        A8 -|5      20|- /BUS 
        A9 -|6      19|- /PICINTA 
       A11 -|7      18|- /PICCS 
       A10 -|8      17|- SR0 
    BUSERR -|9      16|- SR1 
       ALE -|10     15|- RDY 
    CLKOUT -|11     14|- /XACK 
       GND -|12     13|- Gnd 
             - - - - -
                                                                    ibc196.rpt 
**OUTPUTS** 

      Name  Pin  Resource  MCell  PTerms  | Sync Clock
 
      /BUS   20      CONF      3    1/ 8  |     -     
    /PICCS   18      CONF      5    1/ 8  |     -     
  /PICINTA   19      CONF      4    1/ 8  |     -     
      /RAM   22      CONF      1    1/ 8  |     -     
       RDY   15      CONF      8    6/ 8  |     -     
      /ROM   21      CONF      2    3/ 8  |     -     
       SR0   17      RORF      6    1/ 8  |     -     
       SR1   16      RORF      7    1/ 8  |     -     

 
**INPUTS** 

      Name  Pin  Resource  MCell  PTerms  | Sync Clock
 
       ALE   10       INP     16    0/ 8  |     -     
        A8    5       INP     11    0/ 8  |     -     
        A9    6       INP     12    0/ 8  |     -     
       A10    8       INP     14    0/ 8  |     -     
       A11    7       INP     13    0/ 8  |     -     
       A12    3       INP      9    0/ 8  |     -     
       A13    4       INP     10    0/ 8  |     -     
       A14   23       INP      -     -    |     -     
       A15    2       INP      -     -    |     -     
    BUSERR    9       INP     15    0/ 8  |     -     
    CLKOUT   11       INP      -     -    |     -     
     /XACK   14       INP      -     -    |     -     

 
**PART UTILIZATION**
 
 8/ 8  MacroCells (100%)
12/12  Input Pins (100%)
       PTerms Used 23%
Macrocell Interconnection Cross Reference                           ibc196.rpt 

FEEDBACKS:                             
                       M M M M M M M M 
                       1 2 3 4 5 6 7 8 
/RAM ..... CONF @M1 -> . . . . . . . . @22
/ROM ..... CONF @M2 -> . . . . . . . . @21
/BUS ..... CONF @M3 -> . . . . . . . . @20
/PICINTA . CONF @M4 -> . . . . . . . . @19
/PICCS ... CONF @M5 -> . . . . . . . . @18
SR0 ...... RORF @M6 -> . . . . . . * * @17
SR1 ...... RORF @M7 -> . . . . . . . * @16
RDY ...... CONF @M8 -> . . . . . . . . @15


INPUTS:
 
A15 ...... INP  @2  -> * * * * * . . *
A12 ...... INP  @3  -> . . * * * . . * M9 
A13 ...... INP  @4  -> * * * * * . . * M10
A8 ....... INP  @5  -> . . * * * . . * M11
A9 ....... INP  @6  -> . . * * * . . * M12
A11 ...... INP  @7  -> . . * * * . . * M13
A10 ...... INP  @8  -> . . * * * . . * M14
BUSERR ... INP  @9  -> . . . . . . . * M15
ALE ...... INP  @10 -> . . . . . * * . M16
CLKOUT ... INP  @11 -> . . . . . * * .
/XACK .... INP  @14 -> . . . . . . . *
A14 ...... INP  @23 -> * * * * * . . *
                       / / / / / S S R 
                       R R B P P R R D 
                       A O U I I 0 1 Y 
                       M M S C C       
                             I C       
                             N S       
                             T         
                             A         
                                       
                                       
