Michael B. Matthews
MBARI
June 8, 1993
4024
rev 1.0
EP1800
IBC quad ADC board - first release

%*********************************************************************%

OPTIONS: SECURITY = OFF, TURBO = OFF
PART: EP1810J

INPUTS: /A0@51, /A1@14, /A2@15, /A3@16, /A4@20, /A5@21, /A6@22, /A7@23,
	D0@24, D1@25, D2@26,
	SDATA1@36, SCLK1@37, /DRDY1@38, 
	SDATA2@39, SCLK2@40, /DRDY2@41,
	SDATA3@42, SCLK3@43, /DRDY3@44,
	SDATA4@48, SCLK4@49, /DRDY4@50,
	S0@56, S1@55,
	/IORC@11, /IOWC@12, /CCLK@53, /INIT@54,
	CLK1@17, CLK2@19, SHIN@2

OUTPUTS: INT@61, /XENB@67, B0@57, B1@58, B2@59,
	D0@24, D1@25, D2@26, D3@27, D4@28, D5@29, D6@30, D7@31, 
	D8@10, D9@9, D10@8, D11@7, D12@6, D13@5, D14@4, D15@3,
	SDATA@45, SCLK@46, /DRDY@47,
	/PWR@65, XACK1@64, XACK2@63, BRDSEL@13, CLR@68, SHOUT@32, STROBE@62,
	/SCLKENB@60

%*********************************************************************%

NETWORK:

% address bits A0 - A7 %
nA0 = INP(/A0)
A0 = NOT(nA0)
nA1 = INP(/A1)
A1 = NOT(nA1)
nA2 = INP(/A2)
A2 = NOT(nA2)
nA3 = INP(/A3)
A3 = NOT(nA3)
nA4 = INP(/A4)
A4 = NOT(nA4)
nA5 = INP(/A5)
A5 = NOT(nA5)
nA6 = INP(/A6)
A6 = NOT(nA6)
nA7 = INP(/A7)
A7 = NOT(nA7)

% data bits D0 - D2 %
D0 = INP(D0)
D1 = INP(D1)
D2 = INP(D2)

% CLK1 and CLK2 are tied together externally %
% and are sourced from the selected SCLK output % 
CLK1 = INP(CLK1)
CLK2 = INP(CLK2)

% board select jumper inputs %
S0 = INP(S0)	
S1 = INP(S1)

nINIT = INP(/INIT)	% bus initialize line %
INIT = NOT(nINIT)

nIORC = INP(/IORC)	% bus I/O read command %
IORC = NOT(nIORC)

nIOWC = INP(/IOWC)	% bus I/O write command %
IOWC = NOT(nIOWC)

nCCLK = INP(/CCLK)	% system clock %

nPWR = NOT(PWR)
/PWR = CONF(nPWR, VCC)		% power-down pin %

% serial clock inputs %
SCLK1 = INP(SCLK1)
SCLK2 = INP(SCLK2)
SCLK3 = INP(SCLK3)
SCLK4 = INP(SCLK4)

% serial data inputs %
SDATA1 = INP(SDATA1)
SDATA2 = INP(SDATA2)
SDATA3 = INP(SDATA3)
SDATA4 = INP(SDATA4)

% data ready inputs %
nDRDY1 = INP(/DRDY1)
DRDY1 = NOT(nDRDY1)
nDRDY2 = INP(/DRDY2)
DRDY2 = NOT(nDRDY2)
nDRDY3 = INP(/DRDY3)
DRDY3 = NOT(nDRDY3)
nDRDY4 = INP(/DRDY4)
DRDY4 = NOT(nDRDY4)

% MUX outputs %
SDATA, SDATA = COCF(SDATAc, VCC)	% selected serial data line %
nSDATA = NOT(SDATA)
SCLK = CONF(SCLKc, VCC)			% selected serial clock %
nDRDYc = NOT(DRDYc)
/DRDY, nDRDY = COCF(nDRDYc, VCC)	% selected data ready line %

% various other signals %
BRDSEL, BRDSEL = COCF(BRDSELc, VCC)
STROBE, STROBE = COCF(STROBEc, VCC)
nSTROBE = NOT(STROBE)
nXENBc = NOT(XENBc)
/XENB, /XENB = COCF(nXENBc, VCC)
XENB = NOT(/XENB)
CLR, CLR = COCF(CLRc, VCC)
nCLR = NOT(CLR)
SCLKENB = NOT(nSCLKENB)
nINT = NOT(INT)

% low byte of the 16-bit shift regsiter %
D0,  D0f  = RORF(SDATA, CLK2, INIT, GND, OE0)	% stage 1 %
D1,  D1f  = RORF(D0f, CLK2, INIT, GND, OE0)	% stage 2 %
D2,  D2f  = RORF(D1f, CLK2, INIT, GND, OE0)	% stage 3 %
D3,  D3f  = RORF(D2f, CLK2, INIT, GND, OE0)	% stage 4 %
D4,  D4f  = RORF(D3f, CLK2, INIT, GND, OE0)	% stage 5 %
D5,  D5f  = RORF(D4f, CLK2, INIT, GND, OE0)	% stage 6 %
D6,  D6f  = RORF(D5f, CLK2, INIT, GND, OE0)	% stage 7 %
D7,  D7f  = RORF(D6f, CLK2, INIT, GND, OE0)	% stage 8 %

% The D7 output bit is routed externally to Quadrant A from Quadrant B %
SHOUT = CONF(D7f, VCC)
SHIN = INP(SHIN)

% high byte of the 16-bit shift regsiter %
D8,  D8f  = RORF(SHIN, CLK1, INIT, GND, OE1)	% stage 9 %
D9,  D9f  = RORF(D8f,  CLK1, INIT, GND, OE1)	% stage 10 %
D10, D10f = RORF(D9f,  CLK1, INIT, GND, OE1)	% stage 11 %
D11, D11f = RORF(D10f, CLK1, INIT, GND, OE1)	% stage 12 %
D12, D12f = RORF(D11f, CLK1, INIT, GND, OE1)	% stage 13 %
D13, D13f = RORF(D12f, CLK1, INIT, GND, OE1)	% stage 14 %
D14, D14f = RORF(D13f, CLK1, INIT, GND, OE1)	% stage 15 %
D15, D15f = RORF(D14f, CLK1, INIT, GND, OE1)	% stage 16 %

% wait-state machine creates two wait states %
XACK1, XACK1 = RORF(VCC, nCCLK, /XENB, GND, VCC)	
XACK2, XACK2 = RORF(XACK1, nCCLK, /XENB, GND, VCC)	

% interrupt state machine %
INT, INT = RORF(INTENB, nSCLKENB, CLR, GND, VCC) 
/SCLKENB, nSCLKENB = JOJF(INTENB, nDRDY, nINT, INIT, GND, VCC)

% data latch for channel select %
B0, B0 = RORF(D0, nSTROBE, INIT, GND, VCC)
B1, B1 = RORF(D1, nSTROBE, INIT, GND, VCC)
B2, B2 = RORF(D2, nSTROBE, INIT, GND, VCC)

%*********************************************************************%

EQUATIONS:

CLRc = XENB + INIT;
STROBEc = BRDSEL & IOWC;
XENBc = BRDSELc & (IORC + IOWC);
INTENB = (CHANNEL1 + CHANNEL2 + CHANNEL3 + CHANNEL4) * nCLR;

BRDSELc = (/A7 &  A6 & /A5 &  A4 & /A3 & /A2 & /A1 & /S1 & /S0)
	+ (/A7 &  A6 & /A5 &  A4 & /A3 & /A2 &  A1 & /S1 &  S0)	
	+ (/A7 &  A6 & /A5 &  A4 & /A3 &  A2 & /A1 &  S1 & /S0)	
	+ (/A7 &  A6 & /A5 &  A4 & /A3 &  A2 &  A1 &  S1 &  S0);

% shift register high and low byte output enables %
OE0 = BRDSEL & IORC & /A0;
OE1 = BRDSEL & IORC &  A0;

% channel select logic %
PWR      = /B2 & /B1 & /B0;
CHANNEL1 = /B2 & /B1 &  B0;
CHANNEL2 = /B2 &  B1 & /B0;
CHANNEL3 = /B2 &  B1 &  B0;
CHANNEL4 =  B2 & /B1 & /B0;

% Signals SDATAi, SCLKi, and DRDYi (i=1,2,3,4), are MUXed according to the %
% channel select from the channel-select registers B0, B1 and B2.          %

% serial data select %
SDATAc =  (SDATA1 & CHANNEL1)	
	+ (SDATA2 & CHANNEL2)
	+ (SDATA3 & CHANNEL3)
	+ (SDATA4 & CHANNEL4);

% The selected serial clock is disabled high when INT is set so that the %
% serial data stays stationary during an interrupt service. Note that the %
% serial clock line goes tristate at the end of last clock period; hence, %
% all serial clock pins must be pulled high at their inputs		%

% serial clock channel select logic %
SCLKc = ( (SCLK1 & CHANNEL1)
	+ (SCLK2 & CHANNEL2)
	+ (SCLK3 & CHANNEL3)
	+ (SCLK4 & CHANNEL4)) & SCLKENB;
					
% data ready channel select logic %
DRDYc =   (DRDY1 & CHANNEL1)
	+ (DRDY2 & CHANNEL2)
	+ (DRDY3 & CHANNEL3)
	+ (DRDY4 & CHANNEL4);

%*********************************************************************%

END$