&lo6D(8U(s3t12vpsb10H&l66p0e0L&a-3R&a1080V
&a+780H(s3BThe IBC Quad Analog-to-Digital Conversion Board(s0B
&a+780HMichael B. Matthews
&a+780HVersion 2, June 3, 1193

&a+780H(s3BIntroduction(s0B
&a+780HThis document describes the design of the MBARI IBC Quad
&a+780HA/D-Conversion Board. Hereafter, we will refer to this board
&a+780Has the "ADC board". The ADC board provides four isolated 16-
&a+780Hbit analog-to-digital channels based on the CS5501 delta-
&a+780Hsigma A/D-converter. The sample rate of each analog channel
&a+780His approximately 4kHz; however, because of subsampling and
&a+780Hdigital filtering in the delta-sigma converter, the
&a+780Hbandwidth of each channel is limited to approximately 10Hz
&a+780Hwith a 6-pole digital low-pass filter. In other words,
&a+780Halthough data can be read from the converter at a rate of
&a+780H4kHz, the bandwidth of such data is only 10Hz with a -
&a+780H36dB/octave rolloff. This oversamplng/decimation technique
&a+780Hobviates the need for antialiasing filtering before the
&a+780Hconverter.

&a+780H(s3BPhysical Characteristics(s0B
&a+780HThe ADC board requires one 6-inch IBC backplane slot. The
&a+780Hhighest component on the board is 0.5 inches.

&a+780H(s3BPower Requirements(s0B
&a+780HThe ADC board requires +5V at approximately 150mA.

&a+780H(s3BAnalog Section(s0B
&a+780HThere are four isolated analog channels each with its own
&a+780H+/-5V power source. Each channel has separate digital and
&a+780Hanalog ground planes; these planes are connected by zero-ohm
&a+780Hresistors R53, R54, R55, R56 in the form of jumper blocks.
&a+780HThe input range of each channel can be configured as shown
&a+780Hin Table 1. The resistor and jumper designations are given
&a+780Hfor Channel 1 for R66, R67, and jumper JP14; a similar
&a+780Hconfiguration is understood with respect to Channels 2,3,
&a+780Hand 4 (see schematic diagram). [Note that Pin 1 of JP12,
&a+780HJP13, and JP14 is the bottom-most pin; Pin 1 of JP15 is the
&a+780Hbottom-most pin.]

&a+780H(s1S&dDinput range     R66     R67     mode (JP14)(s0S&d@
&a+780H(s1S(0,+2.5V)       none    none    JP14-2,3 unipolar(s0S
&a+780H(s1S(0,+5.0V)       10.03k  none    JP14-2,3 unipolar(s0S
&a+780H(s1S(-2.5,+2.5V)    none    none    JP14-1,2 bipolar(s0S
&a+780H(s1S(-2.5,+2.5V)    none    10.03k  JP14-2,3 unipolar(s0S
&a+780H(s1S(-5.0,+5.0V)    10.03k  none    JP14-1,2 bipolar(s0S

&a+780H(s1S                    Table 1(s0S

&a+780HEach channel is accurate to 14bits. Note that the input
&a+780Hvoltage is limited to +/-5V because of overvoltage
&a+780Hprotection circuitry. When the analog power is shut down,&a840V
&a+780HFET's Q3, Q4, Q5, and Q5 are turned on, thus shorting the
&a+780Hinput voltage to ground and preventing a lockup condition in
&a+780Hthe A/D-converter. Each isolated analog channel contains a
&a+780HCS5501 16-bit serial A/D-converter which provides a serial
&a+780Hdata signal SDATAi, a serial clock signal SCLKi, and a data
&a+780Hready signal DRDYi* for i=1,2,3,4. These signals are passed
&a+780Hto the nonisolated side, i.e., to the side common to the IBC
&a+780Hcommon, by means of optoisolators.

&a+780H(s3BIBC Interface(s0B
&a+780HThe Altera EP1800 EPLD (U1) serves as a 4-to-1 data
&a+780Hmultiplexer, an address decoder, a wait-state machine, a 16-
&a+780Hbit shift register, as well as an interrupt controller. The
&a+780HEPLD uses address bits A0 - A7 in conjuction with the
&a+780Hjumper-selectable inputs S0 and S1 to select the ADC board
&a+780Hat hexidecimal addresses 50, 52, 54 or 56. Table 2 shows the
&a+780Hdecoded address as a function of the jumper position JP17.

&a+780H(s1S&dDaddress         jumpers(s0S&d@
&a+780H(s1S50-51      JP17-1,2  JP17-3,4(s0S
&a+780H(s1S52-53                JP17-3,4(s0S
&a+780H(s1S54-55      JP17-1,2(s0S
&a+780H(s1S56-57           none(s0S

&a+780H(s1S        Table 2(s0S

&a+780HThe BRDSEL output goes high when the ADC board is selected.
&a+780HThe EPLD has a 3-bit command register which stores IBC-bus
&a+780Hdata bits D0, D1, D2 on a write to the ADC board, i.e., on
&a+780Hthe rising edge of IOWC* when BRDSEL is high. The 4-to-1
&a+780Hdata multiplexer uses the command register bits to select
&a+780Hone set of three input signals (SDATAi, SCLKi, DRDYi* for
&a+780Hi=1,2,3,4) from the four serial data channels coming from
&a+780Hthe A/D-converters. Table 3 shows the multiplexer output as
&a+780Ha function of the command register.

&a+780H(s1S&dDcommand register bits     function(s0S&d@
&a+780H(s1S&dD     D2 D1 D2(s0S&d@
&a+780H(s1S     0  0  0              PWR - power down(s0S
&a+780H(s1S     0  0  1              channel 1(s0S
&a+780H(s1S     0  1  0              channel 2(s0S
&a+780H(s1S     0  1  1              channel 3(s0S
&a+780H(s1S     1  0  0              channel 4(s0S
&a+780H(s1S     1  0  1              deselect(s0S
&a+780H(s1S     1  1  0              deselect(s0S
&a+780H(s1S     1  1  1              deselect(s0S

&a+780H(s1S             Table 3(s0S

&a+780HDeselect means that all channels are powered up but no
&a+780Hchannel is selected. An interrupt INT is asserted on the
&a+780Hrising edge of DRDY, indicating that data is ready for
&a+780Hreading. The selected serial clock SCLK is disabled by
&a+780HSCLKENB during an interrupt to prevent new data from being&a840V
&a+780Hclocked into the shift register before the CPU has read the
&a+780Hold data. This will be explained in detail shortly. PWR is
&a+780Hused to power-down the analog power supply.

&a+780HThe selected data output SDATA is fed to a 16-bit shift
&a+780Hregister. The shift register synchronous clock comes from
&a+780Hthe CLK1 and CLK2 synchronous clock inputs, which are tied
&a+780Htogether and connected externally to the selected serial
&a+780Hclock output SCLK. The serial data is clocked into the shift
&a+780Hregister on the rising edge of SCLK. Note that the shift
&a+780Hregister clock cannot be acquired internally from SCLK as an
&a+780Hasynchronous clock because the asynchronous clock line is
&a+780Hused for the shift register output enable. The 16-bit serial
&a+780Hdata from the CS5501 A/D converter is such that the MSB is
&a+780Hsent first and the LSB is sent last. Because the high and
&a+780Hlow bytes of the shift register are separated between
&a+780HQuadrants A and B in the EPLD, the D7 output from Quadrant B
&a+780His routed externally to the D8 input in Quadrant A via SHOUT
&a+780Hand  SHIN. This is necessary because, even though output D7
&a+780Hcan be routed to D8 internally, in the EP1800 EPLD only the
&a+780Houtput side of the tristate buffer can be used as global
&a+780Hfeedback and we require that all shift register outputs be
&a+780Htristate. The shift register is cleared by an active INIT*
&a+780Hinput. Finally, the shift register outputs D0-D7 and D8-D15
&a+780Hare connected together on the data bus. They are enabled
&a+780Honto the data bus by the low-byte and high-byte output
&a+780Henable signals OE0 and OE1, respectively.

&a+780HThe wait-state machine is comprised of two cascaded D-type
&a+780Hflip-flops clocked by the system clock nCCLK. The XACK2
&a+780Houtput goes high after two clock cycles of CCLK* when the
&a+780HADC board is selected and either IORC* or IOWR* is active,
&a+780Hi.e., when /XENB is low.

&a+780H(s3BInterrupts(s0B
&a+780HAn interrupt is asserted at INT on the rising edge of DRDY*
&a+780Hindicating that the data is ready for reading. The interrupt
&a+780Houtput INT is connected to any one of eight system
&a+780Hinterrupts on the IBC backplane via jumper JP16 (jumper
&a+780Hpositions correspond sequentially from left to right to
&a+780Hinterrupt lines INT0-INT7). The interrupt state machine is
&a+780Hcomprised of two flip-flops. When a channel is selected
&a+780H(INTENB high), the JK flip-flop output /SCLKENB is set high
&a+780Hon the rising edge of DRDY* thus disabling the serial clock
&a+780Hand preventing data from being clocked into the shift
&a+780Hregister during the next conversion/transmission cycle. The
&a+780Hrising edge of /SCLKENB in turn sets the interrupt flip-flop
&a+780HINT high signaling an interrupt to the system. All
&a+780Hsubsequent transitions ofDRDY* have no effect and the shift
&a+780Hregister data is held until the CPU reads it. A CPU read
&a+780Hcaused the INT flip-flop to be reset by CLR, thus setting
&a+780Hthe K input of the /SCLKENB JK-flip-flop high. The /SCLKENB
&a+780Hflip-flop is then reset on the next rising edge of DRDY*.
&a+780HThe purpose of this mechanism is to disable the serial clock&a840V
&a+780Hduring the period before the data is read by the CPU. After
&a+780Hthe data is read, the serial clock remains disabled until
&a+780Hthe next DRDY* transition. This is done so that, if the CPU
&a+780Hreads the data during a period where DRDY* is low, the
&a+780Hinterrupt is not set on the subsequent rising edge of DRDY*
&a+780Hwhere no new data is available.

&a+780HThe IBC CPU interrogates the  ADC board as follows: The IBC
&a+780HCPU selects a channel by writing to the command register as
&a+780Hper Table 3; this enables the interrupt. An interrupt occurs
&a+780Hwhen the next data word from that channel is ready. The CPU
&a+780Hperforms a word read to access the data; this clears the
&a+780Hinterrupt. Another interrupt occurs at the end of the next
&a+780Hfull conversion cycle after the read.

&a+780H(s3BAssembly and Modifications(s0B
&a+780HIn first version of the QUAD ADC printed wire board
&a+780H(4024PWB-00) the INT and /SCLKENB outputs of the EPLD U28
&a+780Hwere wired incorrectly. To correct this problem, the circuit
&a+780Htrace running from U28 pin 60 to the gate of Q7 should be
&a+780Hcut, and a jumper wire from U28 pin 61 to the gate of Q7
&a+780Hshould be installed. Note that this cannot be corrected in
&a+780Hthe EPLD because pin 61 does not have global feedback
&a+780Hrequired for /SCLKENB.

&a+780HThe ADC board was design such that the resistor/zener-diode
&a+780Hpairs (R6,D25), (R8,D26), (R10,D27), and (R12,D28) can be
&a+780Hreplaced by a TO-92 low-dropout regulator LM2950A; the diode
&a+780His left out and the regulator is inserted into the resistor
&a+780Hholes with pin 1 at the top (i.e., the flat face of the TO-
&a+780H92 facing toward the EPLD), pin 2 in the unused middle hole,
&a+780Hand pin 3 at the bottom.

&a+780HThe 20-pin I.C. socket footprint U29 is provided as a spare
&a+780Hfor future modifications. Power and ground are not
&a+780Hconnected.

&a+780HAfter soldering, cylindrical crystals Y1, Y2, Y3, and Y4
&a+780Hshould be reinforced to the board at their base with a small
&a+780Hamount of epoxy.

&a+780HResistors R75, R76, and R77 each consist of four 1.5K
&a+780Hdiscrete resistors. Obtaining a resistor SIP for these
&a+780Hproved to be unnecessarily difficult; hence, individual 1/8W
&a+780Hresistors mounted vertically is the next best solution.&a2400V
&a+780H(s3BQuad ADC Board Configuration Template(s0B

&a+780HDate:

&a+780HApplication:

&a+780HSerial Number:

&a+780HRevision:

&a+780HEPLD Revision:

&a+780HInput Configuration (JP12, 13, 14, 15; see Table 1):

&a+780H&dDChannel           1      2      3      4&d@
&a+780Hmode
&a+780Hinput range

&a+780HAddress Selection (JP17 see Table 2):

&a+780HInterrupt Selection (INT0 - INT7 from right to left on
&a+780HJP16):&l0o3e1H