/******************************************************************************/ /* Copyright 1994 MBARI */ /******************************************************************************/ /* Summary : Pan & Tilt Daughter Board Uart Driver */ /* Filename : scc2692.h */ /* Author : Andrew Pearce */ /* Project : Tiburon ROV */ /* Version : Version 1.0 */ /* Created : 04/05/94 */ /* Modified : 04/08/94 */ /* Archived : */ /******************************************************************************/ #ifndef SCC2696_H #define SCC2696_H /**************** SCC2692 DUAL UART Control/Status Registers *****************/ #define MODE_REG0 0x00 /* Mode Register 0: Read/Write */ #define MODE_REG1 0x00 /* Mode Register 1: Read/Write */ #define MODE_REG2 0x00 /* Mode Register 2: Read/Write */ #define STATUS_REG 0x01 /* Channel Status Register: Read Only */ #define CLK_SEL_REG 0x01 /* Clock Select Register: Write Only */ #define COMMAND_REG 0x02 /* Command Register: Write Only */ #define RX_HOLD_REG 0x03 /* Receive Holding Reg: Read Only */ #define TX_HOLD_REG 0x03 /* Transmit Holding Reg: Write Only */ #define IN_CHNG_REG 0x04 /* Input Port Change Reg: Read Only */ #define AUX_CTRL_REG 0x04 /* Auxiliary Control Reg: Write Only */ #define INT_STAT_REG 0x05 /* Interrupt Status Reg: Read Only */ #define INT_MASK_REG 0x05 /* Interrupt Mask Reg: Write Only */ #define CT_UPPER_REG 0x06 /* Counter/Timer High Byte: Read/Write */ #define CT_LOWER_REG 0x07 /* Counter/Timer Low Byte: Read/Write */ #define IN_PORT_REG 0x0d /* Input Port: Read Only */ #define OUT_CONFIG_REG 0x0d /* Output Port Configuration: Write Only */ #define START_TIMER 0x0e /* Start Timer/Counter: Read Only */ #define SET_OUT_PORT 0x0e /* Set Output Port Bits: Write Only */ #define STOP_TIMER 0x0f /* Stop Timer/Counter: Read Only */ #define RESET_OUT_PORT 0x0f /* Reset Output Port Bits: Write Only */ /* ******** SCC2692 Mode Control Register 0 Bits ********* */ #define BAUD_RATE_NORM 0x00 /* Normal Baud Rate Select */ #define BAUD_RATE_EXT 0x01 /* Extended Baud Rate Select*/ #define TxINT_TxEMPTY 0x00 /* Interrupt on Tx Empty */ #define TxINT_TxRDY 0x30 /* Interrupt on Tx Ready */ #define TxINT_8_BYTES 0x00 /* Interrupt on 8 bytes free*/ #define TxINT_4_BYTES 0x10 /* Interrupt on 4 bytes free*/ #define TxINT_6_BYTES 0x20 /* Interrupt on 6 bytes free*/ #define TxINT_1_BYTE 0x30 /* Interrupt on 1 byte free*/ #define RxINT_1_OR_3 0x00 /* Interrupt on 1 or 3 bytes*/ #define RxINT_6_OR_8 0x40 /* Interrupt on 6 or 8 bytes*/ #define WATCHDOG_OFF 0x00 /* Disable Receiver Watchdog*/ #define WATCHDOG_ON 0x80 /* Enable Receiver Watchdog */ /* ******** SCC2692 Mode Control Register 1 Bits ********* */ #define CS5 0x00 /* Character Size = 5 Bits */ #define CS6 0x01 /* Character Size = 6 Bits */ #define CS7 0x02 /* Character Size = 7 Bits */ #define CS8 0x03 /* Character Size = 8 Bits */ #define PAREVEN 0x00 /* Even Parity */ #define PARODD 0x04 /* Odd Parity */ #define PAR_FORCE_EVEN 0x08 /* Force Even Parity */ #define PAR_FORCE_ODD 0x0c /* Force Odd Parity */ #define PARNONE 0x10 /* No Parity */ #define MULTIDROP_MOD 0x18 /* Multidrop mode */ #define CHAR_ERR_MODE 0x00 /* Character Error Mode */ #define BLOCK_ERR_MODE 0x20 /* Block Error Mode */ #define RxINT_RxREADY 0x00 /* Rx Interrupt on Receive Status */ #define RxINT_RxFFULL 0x40 /* Rx Interrupt on FIFO Full */ #define RxRTS_OFF 0x00 /* RTS Deactivated by Software */ #define RxRTS_ON 0x80 /* RTS Deactivated when FIFO full */ /* ******** SCC2692 Mode Control Register 2 Bits ********* */ #define CSTOPB1 0x07 /* Send 1 Stop Bit */ #define CSTOPB2 0x0F /* Send 2 Stop Bits */ #define TxCTS_OFF 0x00 /* Ignore State of CTS line for Tx */ #define TxCTS_ON 0x10 /* Check State of CTS line for Tx */ #define TxRTS_OFF 0x00 /* Don't change state of RTS line on Tx */ #define TxRTS_ON 0x20 /* Clear RTS line after last bit is sent*/ #define CHAN_NORMAL 0x00 /* Channel Operating Mode */ #define CHAN_LOOPBACK 0x80 /* Select Local Loopback Mode */ /* ************ SCC2692 Clock Select Register Bits ************ */ /* NOTE: Bits 0-3 are written to Clock Select Reg (CLK_SEL_REG) */ /* Bit 4 is written to Auxiluary Control Reg (AUX_CTRL_REG)*/ /*****************************************************************/ #define B50 0x00 /* 50 baud */ #define B75 0x10 /* 75 baud */ #define B110 0x11 /* 110 baud */ #define B134 0x02 /* 134 baud */ #define B150 0x13 /* 150 baud */ #define B200 0x03 /* 200 baud */ #define B300 0x14 /* 300 baud */ #define B600 0x15 /* 600 baud */ #define B1200 0x16 /* 1200 baud */ #define B1800 0x1A /* 1800 baud */ #define B2400 0x18 /* 2400 baud */ #define B4800 0x19 /* 4800 baud */ #define B9600 0x1B /* 9600 baud */ #define B19200 0x1C /* 19200 baud */ #define B38400 0x0C /* 38400 baud */ #define BTIMER 0x0D /* Timer Mode */ #define IPx16 0x0E /* Input4 X 16*/ /* ************** SC2692 Command Register Commands *************** */ #define RX_ENABLE 0x01 /* Enable Receiver */ #define RX_DISABLE 0x02 /* Disable Receiver */ #define TX_ENABLE 0x04 /* Enable Transmitter */ #define TX_DISABLE 0x08 /* Disable Transmitter */ #define NO_COMMAND 0x00 /* NOP */ #define RESET_MR1 0x10 /* Reset pointer to Mode Reg 1 */ #define RESET_RX 0x20 /* Reset Receiver */ #define RESET_TX 0x30 /* Reset Transmitter */ #define RESET_ERROR 0x40 /* Reset Error Status */ #define RESET_BREAK 0x50 /* Reset Chan A Break change intr */ #define START_BREAK 0x60 /* Start transmitting a Break */ #define STOP_BREAK 0x70 /* Stop transmitting a Break */ #define ASSERT_RTSN 0x80 /* Set RTS signal TRUE (low) */ #define NEGATE_RTSN 0x90 /* Set RTS signal FALSE (high) */ #define SET_TIMEOUT 0xA0 /* Set special receive timeout mode */ #define RESET_TIMEOUT 0xC0 /* Clear special timeout mode */ #define POWER_DOWN_ON 0xE0 /* Enable Power Down Mode */ #define POWER_DOWN_OFF 0xF0 /* Disable Power Down Mode */ /* ************ SC2692 Channel Status Bits *************** */ #define RxRDY 0x01 /* Receiver is Ready (Byte received)*/ #define RxFFULL 0x02 /* Receive fifo is full */ #define TxRDY 0x04 /* Transmitter is Ready (THR Empty) */ #define TxEMT 0x08 /* Transmitter is Empty (THR & TSR) */ #define RxOVERRUN_ERR 0x10 /* Receive shift register overrun */ #define RxPARITY_ERR 0x20 /* Byte received with parity error */ #define RxFRAMING_ERR 0x40 /* Byte received with framing error */ #define RxBREAK 0x80 /* Received a Break */ /* ******** SC2692 Output Port Configuration Register ******** */ #define OP_MAP_TO_OPR 0x00 #define OP2_OPR2 0x00 #define OP2_TxCLKA_x16 0x01 #define OP2_TxCLKA_x1 0x02 #define OP2_RxCLKA_x1 0x03 #define OP3_OPR3 0x00 #define OP3_CT_OUTPUT 0x04 #define OP3_TxCLKB_x1 0x08 #define OP3_RxCLKB_x1 0x0C #define OP4_OPR4 0x00 #define OP4_RxRDYB 0x10 #define OP5_OPR5 0x00 #define OP5_RxRDYB 0x20 #define OP6_OPR6 0x00 #define OP6_TxRDYA 0x40 #define OP7_OPR7 0x00 #define OP7_TxRDYB 0x80 /* ******** SC2692 Auxiliary Control Register Bits ********* */ #define IP0_INT 0x01 /* Enable IP 0 Change-state interrupt */ #define IP1_INT 0x02 /* Enable IP 1 Change-state interrupt */ #define IP2_INT 0x04 /* Enable IP 2 Change-state interrupt */ #define IP3_INT 0x08 /* Enable IP 3 Change-state interrupt */ #define COUNTER_IP2 0x00 /* Counter clocked from IP2 pin */ #define COUNTER_TxCLKA 0x10 /* Counter clocked from Tx Clock A */ #define COUNTER_TxCLKB 0x20 /* Counter clocked from Tx Clock B */ #define COUNTER_CLK_D16 0x30 /* Counter clocked from crystal/16 */ #define TIMER_IP2 0x40 /* Timer clocked from IP2 pin */ #define TIMER_IP2_D16 0x50 /* Timer clocked from IP2 pin/16 */ #define TIMER_EXT_CLK 0x60 /* Timer clocked from external clock */ #define TIMER_CLK_D16 0x70 /* Timer clocked from crystal/16 */ #define BAUD_RATE_MODE 0x80 /* Select Group 0 or Group 1 baud rates*/ /* ******* SC2692 Input Port Change Register ******** */ #define IP0_PIN 0x01 /* IP0 pin mask bit */ #define IP1_PIN 0x02 /* IP1 pin mask bit */ #define IP2_PIN 0x04 /* IP2 pin mask bit */ #define IP3_PIN 0x08 /* IP3 pin mask bit */ #define IP0_CHANGE 0x10 /* IP0 pin change-state mask bit */ #define IP1_CHANGE 0x20 /* IP1 pin change-state mask bit */ #define IP2_CHANGE 0x40 /* IP2 pin change-state mask bit */ #define IP3_CHANGE 0x80 /* IP3 pin change-state mask bit */ /* ******* SC2692 Interrupt Service Register Bits ******* */ #define TxRDYA 0x01 /* Transmitter A Ready Interrupt Bit */ #define RxRDYA 0x02 /* Receiver A Ready Interrupt Bit */ #define BREAK_STATUS_A 0x04 /* Chan A Break Status Changed Interrpt*/ #define COUNTER_RDY 0x08 /* Counter Ready Interrupt Bit */ #define TxRDYB 0x10 /* Transmitter B Ready Interrupt Bit */ #define RxRDYB 0x20 /* Receiver B Ready Interrupt Bit */ #define BREAK_STATUS_B 0x40 /* Chan B Break Status Changed Interrpt*/ #define MPI_PORT_CHNG 0x80 /* Munti Purpose Input Changed Bit */ #define OP0 0x01 /* General Purpose Output Port Bits */ #define OP1 0x02 #define OP2 0x04 #define OP3 0x08 #define OP4 0x10 #define OP5 0x20 #define OP6 0x40 #define OP7 0x80 #endif