/******************************************************************************/ /* Copyright 1991 to 1996 MBARI */ /******************************************************************************/ /* Summary : Signetics SCC2698 UART definitions */ /* Filename : scc2698.h */ /* Author : Andrew Pearce */ /* Project : Tiburon ROV */ /* Version : Version 1.0 */ /* Created : 06/20/91 */ /* Modified : 03/18/96 */ /* Archived : */ /******************************************************************************/ /**************** OCTAL UART SCC2698 Control/Status Registers *****************/ #define MODE_REG1 0x00 /* Mode Register 1: Read/Write */ #define MODE_REG2 0x00 /* Mode Register 2: Read/Write */ #define STATUS_REG 0x01 /* Channel Status Register: Read Only */ #define CLK_SEL_REG 0x01 /* Clock Select Register: Write Only */ #define COMMAND_REG 0x02 /* Command Register: Write Only */ #define RX_HOLD_REG 0x03 /* Receive Holding Reg: Read Only */ #define TX_HOLD_REG 0x03 /* Transmit Holding Reg: Write Only */ #define IN_CHNG_REG 0x04 /* Input Port Change Reg: Read Only */ #define AUX_CTRL_REG 0x04 /* Auxiliary Control Reg: Write Only */ #define INT_STAT_REG 0x05 /* Interrupt Status Reg: Read Only */ #define INT_MASK_REG 0x05 /* Interrupt Mask Reg: Write Only */ #define CT_UPPER_REG 0x06 /* Counter/Timer High Byte: Read/Write */ #define CT_LOWER_REG 0x07 /* Counter/Timer Low Byte: Read/Write */ #define IN_PORT_REG 0x0d /* Input Port chan 0/1: Read Only */ #define OUT_CONFIG_REG 0x0d /* Output Port chan 0/1: Write Only */ #define START_TIMER 0x0e /* Start Timer/Counter: Write Only */ #define STOP_TIMER 0x0f /* Stop Timer/Counter: Write Only */ /* ********** SCC2698 Mode Control Register Bits ********* */ #define CS5 0x00 /* Character Size = 5 Bits */ #define CS6 0x01 /* Character Size = 6 Bits */ #define CS7 0x02 /* Character Size = 7 Bits */ #define CS8 0x03 /* Character Size = 8 Bits */ #define PARNONE 0x10 /* No Parity */ #define PAREVEN 0x00 /* Even Parity */ #define PARODD 0x04 /* Odd Parity */ #define PARWAKEUP 0x18 /* Special Wake Up Mode */ #define CHAR_ERR_MODE 0x00 /* Character Error Mode */ #define BLOCK_ERR_MODE 0x20 /* Block Error Mode */ #define RxINT_RxREADY 0x00 /* Rx Interrupt on Receive Status */ #define RxINT_RxFFULL 0x40 /* Rx Interrupt on FIFO Full */ #define RxRTS_OFF 0x00 /* RTS Deactivated by Software */ #define RxRTS_ON 0x80 /* RTS Deactivated when FIFO full */ #define CSTOPB1 0x07 /* Send 1 Stop Bit */ #define CSTOPB2 0x0F /* Send 2 Stop Bits */ #define TxCTS_OFF 0x00 /* Ignore State of CTS line for Tx */ #define TxCTS_ON 0x10 /* Check State of CTS line for Tx */ #define TxRTS_OFF 0x00 /* Don't change state of RTS line on Tx */ #define TxRTS_ON 0x20 /* Clear RTS line after last bit is sent*/ #define CHAN_NORMAL 0x00 /* Channel Operating Mode */ #define CHAN_LOOPBACK 0x80 /* Select Local Loopback Mode */ /* ************ SCC2698 Clock Select Register Bits ************* */ /* NOTE: Bits 0-3 are written to Clock Select Reg (CLK_SEL_REG) */ /* Bit 4 is written to Auxiluary Control Reg (AUX_CTRL_REG)*/ /*****************************************************************/ #define B50 0x00 /* 50 baud */ #define B75 0x10 /* 75 baud */ #define B110 0x11 /* 110 baud */ #define B134 0x02 /* 134 baud */ #define B150 0x13 /* 150 baud */ #define B200 0x03 /* 200 baud */ #define B300 0x14 /* 300 baud */ #define B600 0x15 /* 600 baud */ #define B1200 0x16 /* 1200 baud */ #define B1800 0x1A /* 1800 baud */ #define B2400 0x18 /* 2400 baud */ #define B4800 0x19 /* 4800 baud */ #define B9600 0x1B /* 9600 baud */ #define B19200 0x1C /* 19200 baud */ #define B38400 0x12 /* 38400 baud */ #define BTIMER 0x0D /* Timer Mode */ /* ************** SC2698 Command Register Commands **************** */ #define RX_ENABLE 0x01 /* Enable Receiver */ #define RX_DISABLE 0x02 /* Disable Receiver */ #define TX_ENABLE 0x04 /* Enable Transmitter */ #define TX_DISABLE 0x08 /* Disable Transmitter */ #define NO_COMMAND 0x00 /* NOP */ #define RESET_MR1 0x10 /* Reset pointer to Mode Reg 1 */ #define RESET_RX 0x20 /* Reset Receiver */ #define RESET_TX 0x30 /* Reset Transmitter */ #define RESET_ERROR 0x40 /* Reset Error Status */ #define RESET_BREAK 0x50 /* Reset Break change interrupt */ #define START_BREAK 0x60 /* Start transmitting a Break */ #define STOP_BREAK 0x70 /* Stop transmitting a Break */ #define ASSERT_RTSN 0x80 /* Set RTS signal TRUE (low) */ #define NEGATE_RTSN 0x90 /* Set RTS signal FALSE (high) */ #define SET_TIMEOUT 0xA0 /* Set special receive timeout mode */ #define RESET_TIMEOUT 0xC0 /* Clear special timeout mode */ /* ************ SC2698 Channel Status Bits *************** */ #define RxRDY 0x01 /* Receiver is Ready (Byte received)*/ #define RxFFULL 0x02 /* Receive fifo is full */ #define TxRDY 0x04 /* Transmitter is Ready (THR Empty) */ #define TxEMT 0x08 /* Transmitter is Empty (THR & TSR) */ #define RxOVERRUN_ERR 0x10 /* Receive shift register overrun */ #define RxPARITY_ERR 0x20 /* Byte received with parity error */ #define RxFRAMING_ERR 0x40 /* Byte received with framing error */ #define RxBREAK 0x80 /* Received a Break */ /* ******** SC2698 Output Port Configuration Register ******** */ #define MPOA_RTSN 0x00 /* MPOA is RTS */ #define MPOA_CT_OUT 0x01 /* MPOA is Counter/Timer output */ #define MPOA_TxCLK_x1 0x02 /* MPOA is 1 x transmit clock */ #define MPOA_TxCLK_x16 0x03 /* MPOA is 16 x transmit clock */ #define MPOA_RxCLK_x1 0x04 /* MPOA is 1 x receive clock */ #define MPOA_RxCLK_x16 0x05 /* MPOA is 16 x receive clock */ #define MPOA_TxRDY 0x06 /* MPOA is transmit reg empty signal*/ #define MPOA_RxRDY 0x07 /* MPOA is receiver ready signal */ #define POWER_DOWN_MODE 0x80 /* Select Power Down Mode */ #define MPOB_RTSN 0x00 /* MPOB is RTS */ #define MPOB_CT_OUT 0x10 /* MPOB is Counter/Timer output */ #define MPOB_TxCLK_x1 0x20 /* MPOB is 1 x transmit clock */ #define MPOB_TxCLK_x16 0x30 /* MPOB is 16 x transmit clock */ #define MPOB_RxCLK_x1 0x40 /* MPOB is 1 x receive clock */ #define MPOB_RxCLK_x16 0x50 /* MPOB is 16 x receive clock */ #define MPOB_TxRDY 0x60 /* MPOB is transmit reg empty signal*/ #define MPOB_RxRDY 0x70 /* MPOB is receiver ready signal */ #define MPP_INPUTS 0x00 /* MPP Pins are inputs */ #define MPP_OUTPUTS 0x80 /* MPP Pins are outputs */ /* ******** SC2698 Auxiliary Control Register Bits ********* */ #define MPI0A_INT 0x01 /* Enable MPI0A Change-state interrupt */ #define MPI1A_INT 0x02 /* Enable MPI1A Change-state interrupt */ #define MPI0B_INT 0x04 /* Enable MPI0B Change-state interrupt */ #define MPI1B_INT 0x08 /* Enable MPI0B Change-state interrupt */ #define COUNTER_MPI 0x00 /* Counter clocked from MPI pin */ #define COUNTER_MPI_D16 0x10 /* Counter clocked from MPI pin/16 */ #define COUNTER_TxCLK 0x20 /* Counter clocked from transmit clock */ #define COUNTER_CLK_D16 0x30 /* Counter clocked from crystal/16 */ #define TIMER_MPI 0x40 /* Timer clocked from MPI pin */ #define TIMER_MPI_D16 0x50 /* Timer clocked from MPI pin/16 */ #define TIMER_EXT_CLK 0x60 /* Timer clocked from external clock */ #define TIMER_CLK_D16 0x70 /* Timer clocked from crystal/16 */ #define BAUD_RATE_MODE 0x80 /* Select Group 0 or Group 1 baud rates*/ /* ******* SC2698 Input Port Change Register ******** */ #define MPI0A_PIN 0x01 /* MPI0A pin mask bit */ #define MPI1A_PIN 0x02 /* MPI1A pin mask bit */ #define MPI0B_PIN 0x04 /* MPI0B pin mask bit */ #define MPI1B_PIN 0x08 /* MPI0B pin mask bit */ #define MPI0A_CHANGE 0x10 /* MPI0A pin change-state mask bit */ #define MPI1A_CHANGE 0x20 /* MPI1A pin change-state mask bit */ #define MPI0B_CHANGE 0x40 /* MPI0B pin change-state mask bit */ #define MPI1B_CHANGE 0x80 /* MPI1B pin change-state mask bit */ /* ******* SC2698 Interrupt Service Register Bits ******* */ #define TxRDYA 0x01 /* Transmitter A Ready Interrupt Bit */ #define RxRDYA 0x02 /* Receiver A Ready Interrupt Bit */ #define BREAK_STATUS_A 0x04 /* Chan A Break Status Changed Interrpt*/ #define COUNTER_RDY 0x08 /* Counter Ready Interrupt Bit */ #define TxRDYB 0x10 /* Transmitter B Ready Interrupt Bit */ #define RxRDYB 0x20 /* Receiver B Ready Interrupt Bit */ #define BREAK_STATUS_B 0x40 /* Chan B Break Status Changed Interrpt*/ #define MPI_PORT_CHNG 0x80 /* Multi Purpose Input Changed Bit */ #define DATA_BITS(num) num - 5 #define STOP_BIT(bits) (bits ? CSTOPB1 : CSTOPB2) #define PARITY(bits) (bits & 0x02 ? PARNONE : (bits & 0x01 ? PARODD : PAREVEN))