;**************************************************************************** ;* Copyright 1990 to 1995 MBARI * ;**************************************************************************** ;* Summary : Assembly language configuration file for 3x5 microcontroller * ;* Filename : config.s * ;* Author : Douglas Au * ;* Project : Tiburon ROV * ;* Version : 1.0 * ;* Created : 02/23/95 * ;* Modified : 03/02/95 * ;* Archived : * ;**************************************************************************** ;* Modification History: ;* $Header: /usr/tiburon/.cvsroot/micro/camera/config.s,v 1.1.1.1 1997/05/02 19:17:18 pean Exp $ ;* $Log: config.s,v $ ;* Revision 1.1.1.1 1997/05/02 19:17:18 pean ;* Initial check in of the camera microcontroller software ;* ; Initial revision ; ;**************************************************************************** ; $TITLE("MBARI Camera Microcontroller Board") ; MICRO MODULE MAIN, STACKSIZE(2000) ; 2000 (Decimal) Byte Stack ; ;********************* Memory address and size ******************************* ; RAM_BASE_ADDR EQU 0C000H ; Base address of external RAM RAM_SIZE EQU 4000H ; Size of RAM in bytes 16384 decimal ; ;******************** Switches for Optional Sub-system Support *************** ; USE_HUMIDITY_SENSOR EQU 1 ; Include Support for Humidity Sensor USE_WATCHDOG_TIMER EQU 0 ; Enable Watch Dog Timer USE_TIMER_CHAIN EQU 1 ; Add timer chain Support EXTRN pwmRate:WORD EXTRN totalPwmRate:WORD EXTRN zoomMotorOffTime:WORD EXTRN focusMotorOffTime:WORD EXTRN port1Image:BYTE EXTRN IOPORT1_COPY:BYTE EXTRN camUartIsr:ENTRY ;********************************************************************* CAM_BIT EQU 0 ; PWM_0_BIT EQU 1 ; PWM_1_BIT EQU 2 ; SYSTEM_BIT EQU 3 ; CAM_FULL_BIT EQU 6 ; ; ;***************************************************************************** RSEG RG0: DSW 1 RG4: DSW 1 RG2 EQU RG0 + 2 : BYTE BYTE_REG0: DSB 1 BYTE_REG1: DSB 1 OLD_HSO_STAT: DSB 1 ; SYNC_TIME: DSW 1 ; RUNNING_TIME: DSW 1 ; servo_time_out: DSW 1 ; ;************************ Interrupt Vector Table ***************************** interrupt_vector_table EQU 2000H ; Address of interrupt table int_vector_table_ext EQU 2030H ; and additional interrupts CSEG AT interrupt_vector_table DCW isr_dummy ; Timer1 Overflow Interrupt Handler DCW isr_dummy ; AD Conversion Interrupt Handler DCW isr_dummy ; HSI Data Available Interrupt Handler DCW hso_int_isr ; HSO Interrupt Handler DCW isr_dummy ; HSI 0 Interrupt Handler DCW software_timer_isr ; Software Timer Interrupt Handler DCW isr_dummy ; Serial Port Interrupt Handler DCW ext_int_isr ; External Interrupt Handler DCW isr_dummy ; Trap Interrupt Handler DCW isr_dummy ; Unimplemented Opcode Handler CSEG AT int_vector_table_ext DCW isr_dummy ; Serial Transmitter Interrupt Handler DCW receiver_isr ; Serial Receiver Interrupt Handler DCW isr_dummy ; HSI Fifo Data Interrupt Handler DCW isr_dummy ; Timer2 Capture Interrupt Handler DCW isr_dummy ; Timer2 Overflow Interrupt Handler DCW isr_dummy ; External Interrupt Handler DCW isr_dummy ; HSI Fifo Full Interrupt Handler DCW isr_dummy ; NMI Interrupt Handler ;*************************************************************************** ; ; CHIP CONFIGURATION BYTE ; ;*************************************************************************** ; chip_configuration_register EQU 2018H ; Address of CCR in ROM ; ; Define Chip Configuration Register: ; Bit 0 = 0: Power Down Mode Disabled ; Bit 1 = 0: Bus Width not controlled by 16/8* Pin ; Bit 2 = 1: WR and BHE Mode ; Bit 3 = 0: ADV Mode ; Bit 4 = 1: Wait States not limited internally ; Bit 5 = 1: Wait States not limited internally ; Bit 6 = 1: EPROM Write Protection Disabled ; Bit 7 = 1: EPROM Read Protection Disabled CSEG AT chip_configuration_register DCB 0F4H ;***************************************************************************** ; push_c_context - macro to save C context for Interrupt Service Routines ; push_c_context MACRO PUSH PLMREG+0 PUSH PLMREG+2 PUSH PLMREG+4 PUSH PLMREG+6 PUSH PLMREG+8 ENDM ; ;***************************************************************************** ; pop_c_context - macro to restore C context for Interrupt Service Routines ; pop_c_context MACRO POP PLMREG+8 POP PLMREG+6 POP PLMREG+4 POP PLMREG+2 POP PLMREG+0 ENDM ; CSEG ;**************************************************************************** ;* Function : ext_int_isr * ;* Purpose : External Interrupt Service Routine * ;* Inputs : None * ;* Outputs : None * ;**************************************************************************** ; ext_int_isr: PUSHA ; Save PSW and INT_MASK1 PUSH PLMREG ; Save register used for vector read EI ; Re-enable '196 Global Interrupts LDB PLMREG,3[SP] ; Fetch saved INT_MASK1 from stack ; Re-enable Serial Port Interrupts ANDB INT_MASK1, PLMREG, #RI_INT_MASK + TI_INT_MASK push_c_context ; Save C Context ext_int_pend: LCALL camUartIsr ; Call Camera Uart ISR JBC IOPORT2, 2, ext_int_rti ; Check if Ext Int still high JBC INT_PEND, 7, ext_int_pend ; If '196 missed PIC interrupt ext_int_rti: pop_c_context ; Restore C Context POP PLMREG POPA RET sw_timer_2_hook: RET sw_timer_3_hook: RET ;**************************************** ;* * ;* scale_mult * ;* * ;**************************************** ; PUBLIC scale_mult ; scale_mult(a,b); scale_mult: ; LD RG0, 2[SP] ; LD RG4, 4[SP] ; MUL RG0, RG4 ; ; CMP RG2, #07Fh ; bounded positive JGT mult_high ; ; CMP RG2, #0FF80H ; bounded negative JLE mult_low ; ; SHRAL RG0, #8 ; ; RET ; ; mult_high: ; LD RG0, #07FFFh ; max positive number RET ; ; mult_low: ; LD RG0, #08000h ; max negative number RET ; ;************************************************ ;* * ;* HIGH SPEED OUTPUTS * ;* * ;************************************************ ; ; There are 3 HSO lines active in this system. ; ; HSO.1 PWM #0 Channel ; ; * When HSO.1 = 0, the PWM #0 is ON ; HSO.1 = 1, the PWM #0 is OFF ; ; * Does not generate an interrupt ; ; * Both ON and OFF intervals must be loaded each ; system period. ; ; ; HSO.2 PWM #1 Channel ; ; * When HSO.2 = 0, the PWM #1 is ON ; HSO.2 = 1, the PWM #1 is OFF ; ; * Does not generate an interrupt ; ; * Both ON and OFF intervals must be loaded each ; system period. ; ; HSO.3 SYSTEM TIMER ; ; * The HSO.3 state toggles between 0 and 1 each cycle ; given an external clock rate of 0.5 the system rate ; ; * An interrupt is generated on each 'edge' of the clock ; ; * The interrupt servicing routine sets HSO.1 and HSO.2 to ; reflect the desired PWM values ; ; ;************************************************ ;* * ;* hso_int_isr * ;* * ;************************************************ hso_int_isr: ; PUSHF ; ; LCALL pulse_width_modulator ; ; POPF ; RET ; ;************************************************ ;* * ;* pulse_width_modulator * ;* * ;************************************************ ; pulse_width_modulator: LD SYNC_TIME, TIMER1 ; Grab Sync-time ANDB BYTE_REG0, IOPORT1_COPY,#11110000B ; LDB BYTE_REG1, port1Image[R0] ANDB BYTE_REG1, #00001111B ; ORB BYTE_REG0, BYTE_REG1 ; LDB IOPORT1_COPY, BYTE_REG0 ; LDB IOPORT1, IOPORT1_COPY ; Set Motor Direction ; PWM1: JBS IOS0, CAM_FULL_BIT, PWM1 ; wait for hso LDB HSO_COMMAND, #00100001B ; HSO.1, SET, NO_INT ADD HSO_TIME, SYNC_TIME, zoomMotorOffTime ; PWM2: JBS IOS0, CAM_FULL_BIT, PWM2 ; wait for hso LDB HSO_COMMAND, #00100010B ; HSO.2, SET, NO_INT ADD HSO_TIME, SYNC_TIME, focusMotorOffTime ; PWM3: JBS IOS0, CAM_FULL_BIT, PWM3 ; wait for hso LDB HSO_COMMAND, #00000001B ; HSO.1, CLR, NO_INT ADD HSO_TIME, SYNC_TIME, pwmRate; ; PWM4: JBS IOS0, CAM_FULL_BIT, PWM4 ; wait for hso LDB HSO_COMMAND, #00000010B ; HSO.2, CLR, NO_INT ADD HSO_TIME, SYNC_TIME, pwmRate ; ; PWM0: JBS IOS0, CAM_FULL_BIT, PWM0 ; wait for hso ; JBS IOS0, SYSTEM_BIT, PWM_REV ; 1st half of clock ; LDB HSO_COMMAND, #00110011B ; HSO.3 = 1 in pwmRate ADD HSO_TIME, SYNC_TIME, totalPwmRate ; BR hso_end ; ; PWM_REV:LDB HSO_COMMAND, #00010011B ; HSO.3 = 0 in pwmRate ADD HSO_TIME, SYNC_TIME, totalPwmRate ; hso_end: ; RET ; ;************************************************ ;* * ;* start_pwm * ;* * ;************************************************ ; PUBLIC start_pwm ; start_pwm: ORB INT_MASK, #HSO_INT_MASK ;Enable HSO interrupts ORB OLD_HSO_STAT,#00001000B ;Intialize OLD_HSO_STATUS LDB HSO_COMMAND, #00010011B ;Clear HSO.3 and cause interrupt ADD HSO_TIME, TIMER1, #500 ; RET ; IF USE_HUMIDITY_SENSOR $INCLUDE(\hardware\micro\humid.s) ENDIF