;****************************************************************************
;* Copyright 1990, 1991, 1992 MBARI                                         *
;****************************************************************************
;* Summary  : Assembly language configuration file for IBC CPU board        *
;* Filename : config.s                                                      *
;* Author   : Andrew Pearce                                                 *
;* Project  : ROV 1.5 IBC CPU board Rev 1.0                                 *
;* Version  : 1.0                                                           *
;* Created  : 04/26/91                                                      *
;* Modified : 09/10/93                                                      *
;* Archived :                                                               *
;****************************************************************************
;* Modification History:
;* $Header: /usr/tiburon/.cvsroot/micro/ibc/boards/cpu196/config.s,v 1.2 1997/05/07 15:26:36 pean Exp $
;* $Log: config.s,v $
;* Revision 1.2  1997/05/07 15:26:36  pean
;* Cleaned up Include files and makefile for new directory structure.
;*
;* Revision 1.1.1.1  1997/05/02 18:51:27  pean
;* Initial check in of IBC microcontroller software
;*
; Revision 1.1  93/07/02  09:22:15  09:22:15  pean (Andrew Pearce)
; Initial revision
;
;Revision 1.2  92/05/19  14:29:21  14:29:21  pean (Andrew Pearce 408-647-3746)
;Added support for analog humidity sensor and 82C59 PIC
;
;
;Revision 1.1  92/05/14  08:11:24  08:11:24  pean (Andrew Pearce 408-647-3746)
;Initial revision
;
;****************************************************************************
;
$TITLE("MBARI IBC CPU Board")
;
MICRO   MODULE MAIN
;
;********************* Memory address and size *******************************
;
RAM_BASE_ADDR   EQU  0E000H     ; Base address of external RAM
RAM_SIZE        EQU   2000H     ; Size of RAM in bytes 8192 decimal
;
;******************** Switches for Optional Sub-system Support ***************
;
USE_WATCHDOG_TIMER  EQU 0       ; Enable Watch Dog Timer
USE_TIMER_CHAIN     EQU 1       ; Add timer chain Support
;
;************************ Interrupt Vector Table *****************************

EXTRN NMI_isr:ENTRY                     ; NMI_isr function in ibc.s
EXTRN ext_int_isr:ENTRY                 ; ext_int_isr function in ibc.s

interrupt_vector_table      EQU 2000H   ; Address of interrupt table
int_vector_table_ext        EQU 2030H   ; and additional interrupts

        CSEG AT interrupt_vector_table

        DCW  isr_dummy                  ; Timer1 Overflow Interrupt Handler
        DCW  isr_dummy                  ; AD Conversion Interrupt Handler
        DCW  isr_dummy                  ; HSI Data Available Interrupt Handler
        DCW  isr_dummy                  ; HSO Interrupt Handler
        DCW  isr_dummy                  ; HSI 0 Interrupt Handler
        DCW  software_timer_isr         ; Software Timer Interrupt Handler
        DCW  isr_dummy                  ; Serial Port Interrupt Handler
        DCW  ext_int_isr                ; External Interrupt Handler
        DCW  isr_dummy                  ; Trap Interrupt Handler
        DCW  isr_dummy                  ; Unimplemented Opcode Handler

        CSEG AT int_vector_table_ext

        DCW  isr_dummy                  ; Serial Transmitter Interrupt Handler
        DCW  receiver_isr               ; Serial Receiver Interrupt Handler
        DCW  isr_dummy                  ; HSI Fifo Data Interrupt Handler
        DCW  isr_dummy                  ; Timer2 Capture Interrupt Handler
        DCW  isr_dummy                  ; Timer2 Overflow Interrupt Handler
        DCW  ext_int_isr                ; External Interrupt Handler
        DCW  isr_dummy                  ; HSI Fifo Full Interrupt Handler
        DCW  NMI_isr                    ; NMI Interrupt Handler

;*****************************************************************************
;
;       CHIP CONFIGURATION BYTE
;
;***************************************************************************
;
chip_configuration_register     EQU     2018H   ; Address of CCR in ROM
;
; Define Chip Configuration Register:
;   Bit 0 = 0: Power Down Mode Disabled
;   Bit 1 = 0: Bus Width controlled by 16/8* Pin
;   Bit 2 = 1: WR and BHE Mode
;   Bit 3 = 0: ADV Mode
;   Bit 4 = 1: Wait States not limited internally
;   Bit 5 = 1: Wait States not limited internally
;   Bit 6 = 1: EPROM Write Protection Disabled
;   Bit 7 = 1: EPROM Read Protection Disabled

        CSEG AT chip_configuration_register
        DCB  0F4H

;*****************************************************************************

    CSEG

sw_timer_2_hook:
    RET

sw_timer_3_hook:                        ; Unused at this time
    RET