/*FILE HEADER************************************************************ * * File Name : $Id$ * RCS Revision Number : $Revision: 1.1 $ * Last Modified : $Date: 94/10/28 09:25:40 $ * Last Modified By : $Author: scoudray $ * CSCI Name : Version 7 Baseline Include File * Notes * This include file contains the literals used for AVICS DARF * and ACC register accesses and bit masks. * History * May 21, 1991 Kathy Eagan * Original release * *END FILE HEADER********************************************************/ #ifdef MAKEHS #undef MAKEHS #include #endif /* * General AVICS definitions. */ #define AVICS_LM_FIFO_SIZE 31 #define AVICS_DATA_FIFO_SIZE 7 /* should use DARF32_DATA_FIFO_SIZE. */ #define DARF32_DATA_FIFO_SIZE 7 #define DARF64_DATA_FIFO_SIZE 15 /* * DARF Register offsets. */ #define DARF_DMASAR_OFFSET 0x00 #define DARF_DMADAR_OFFSET 0x04 #define DARF_DMATC_OFFSET 0x08 #define DARF_DCSR_OFFSET 0x0C #define DARF_VMEBAR_OFFSET 0x10 #define DARF_RXDAT_OFFSET 0x14 #define DARF_RXADD_OFFSET 0x18 #define DARF_RXCNT_OFFSET 0x1C #define DARF_VSBEN_OFFSET 0x20 #define DARF_ISTAT_OFFSET 0x24 #define DARF_WPBR_OFFSET 0x28 #define DARF_DATO_OFFSET 0x2C #define DARF_ADDO_OFFSET 0x30 #define DARF_AMO_OFFSET 0x34 #define DARF_LMR_OFFSET 0x38 #define DARF_DMODE_OFFSET 0x3C #define DARF_SA64BAR_OFFSET 0x40 #define DARF_MA64BAR_OFFSET 0x44 #define DARF_LAGR_OFFSET 0x48 #define DARF_DMASTLR_OFFSET 0x4C /* * DARF CSR masks and offsets. */ #define DARF_DCSR_GO_OFFSET 0 #define DARF_DCSR_DONE_OFFSET 1 #define DARF_DCSR_VBER_OFFSET 2 #define DARF_DCSR_LBER_OFFSET 3 #define DARF_DCSR_LMHD_OFFSET 4 #define DARF_DCSR_DLBER_OFFSET 5 #define DARF_DCSR_TXHD_OFFSET 6 #define DARF_DCSR_RXHD_OFFSET 7 #define DARF_DCSR_TXR_OFFSET 8 #define DARF_DCSR_RXR_OFFSET 9 #define DARF_DCSR_RXSFT_OFFSET 10 #define DARF_DCSR_BARDY_OFFSET 11 #define DARF_DCSR_A64BARDY_OFFSET 12 #define DARF_DCSR_RMCERR_OFFSET 13 #define DARF_DCSR_RETRY_OFFSET 14 #define DARF_DCSR_TXSHFT_OFFSET 15 #define DARF_DCSR_CERR_OFFSET 16 #define DARF_DCSR_DARF64_OFFSET 24 #define DARF_DCSR_GO_MASK 0x00000001 #define DARF_DCSR_DONE_MASK 0x00000002 #define DARF_DCSR_VBER_MASK 0x00000004 #define DARF_DCSR_LBER_MASK 0x00000008 #define DARF_DCSR_LMHD_MASK 0x00000010 #define DARF_DCSR_DLBER_MASK 0x00000020 #define DARF_DCSR_TXHD_MASK 0x00000040 #define DARF_DCSR_RXHD_MASK 0x00000080 #define DARF_DCSR_TXR_MASK 0x00000100 #define DARF_DCSR_RXR_MASK 0x00000200 #define DARF_DCSR_RXSFT_MASK 0x00000400 #define DARF_DCSR_BARDY_MASK 0x00000800 #define DARF_DCSR_A64BARDY_MASK 0x00001000 #define DARF_DCSR_RMCERR_MASK 0x00002000 #define DARF_DCSR_RETRY_MASK 0x00004000 #define DARF_DCSR_TXSHFT_MASK 0x00008000 #define DARF_DCSR_CERR_MASK 0x00010000 #define DARF_DCSR_DARF64_MASK 0xFF000000 /* * DARF DMODE masks and offsets. */ #define DARF_DMODE_VINEN_OFFSET 0 #define DARF_DMODE_PROT_OFFSET 1 #define DARF_DMODE_A16DI_OFFSET 2 #define DARF_DMODE_A24DI_OFFSET 3 #define DARF_DMODE_DISRX_OFFSET 4 #define DARF_DMODE_LOOPBK_OFFSET 5 #define DARF_DMODE_A24P0_OFFSET 6 #define DARF_DMODE_TASCON_OFFSET 7 #define DARF_DMODE_BERRCHK_OFFSET 8 #define DARF_DMODE_DMA24_OFFSET 9 #define DARF_DMODE_A24SLVEN_OFFSET 10 #define DARF_DMODE_TXATOM_OFFSET 11 #define DARF_DMODE_RXATOM_OFFSET 12 #define DARF_DMODE_BLEN_OFFSET 14 #define DARF_DMODE_FIFOBEN_OFFSET 15 #define DARF_DMODE_DMARD_OFFSET 16 #define DARF_DMODE_BLT32_OFFSET 17 #define DARF_DMODE_BLT_OFFSET 18 #define DARF_DMODE_MBLT_OFFSET 19 #define DARF_DMODE_DMAA64_OFFSET 20 #define DARF_DMODE_FILL_OFFSET 21 #define DARF_DMODE_NOREL_OFFSET 22 #define DARF_DMODE_DPRIV_OFFSET 23 #define DARF_DMODE_040_OFFSET 24 #define DARF_DMODE_SWAP_OFFSET 25 #define DARF_DMODE_BUSSIZ_OFFSET 26 #define DARF_DMODE_RMCPIN_OFFSET 27 #define DARF_DMODE_DMABEN_OFFSET 28 #define DARF_DMODE_RMCRTRY_OFFSET 29 #define DARF_DMODE_DARFEN_OFFSET 31 #define DARF_DMODE_VINEN_MASK 0x00000001 #define DARF_DMODE_PROT_MASK 0x00000002 #define DARF_DMODE_RWPM_MASK DARF_DMODE_PROT_MASK /* Compatability */ #define DARF_DMODE_A16DI_MASK 0x00000004 #define DARF_DMODE_A24DI_MASK 0x00000008 #define DARF_DMODE_DISRX_MASK 0x00000010 #define DARF_DMODE_LOOPBK_MASK 0x00000020 #define DARF_DMODE_A24P0_MASK 0x00000040 #define DARF_DMODE_TASCON_MASK 0x00000080 #define DARF_DMODE_BERRCHK_MASK 0x00000100 #define DARF_DMODE_DMA24_MASK 0x00000200 #define DARF_DMODE_A24SLVEN_MASK 0x00000400 #define DARF_DMODE_TXATOM_MASK 0x00000800 #define DARF_DMODE_RXATOM_MASK 0x00001000 #define DARF_DMODE_BLEN_MASK 0x00006000 #define DARF_DMODE_FIFOBEN_MASK 0x00008000 #define DARF_DMODE_DMARD_MASK 0x00010000 #define DARF_DMODE_BLT32_MASK 0x00020000 #define DARF_DMODE_BLT_MASK 0x00040000 #define DARF_DMODE_MBLT_MASK 0x00080000 #define DARF_DMODE_DMAA64_MASK 0x00100000 #define DARF_DMODE_FILL_MASK 0x00200000 #define DARF_DMODE_NOREL_MASK 0x00400000 #define DARF_DMODE_DPRIV_MASK 0x00800000 #define DARF_DMODE_040_MASK 0x01000000 #define DARF_DMODE_SWAP_MASK 0x02000000 #define DARF_DMODE_BUSSIZ_MASK 0x04000000 #define DARF_DMODE_RMCPIN_MASK 0x08000000 #define DARF_DMODE_DMABEN_MASK 0x10000000 #define DARF_DMODE_RMCRTRY_MASK 0x20000000 #define DARF_DMODE_DARFEN_MASK 0x80000000 /* * DARF VMEBAR masks and offsets. */ #define DARF_VMEBAR_A32BA_OFFSET 0 #define DARF_VMEBAR_A32SIZ_OFFSET 5 #define DARF_VMEBAR_A24BA_OFFSET 16 #define DARF_VMEBAR_A24SIZ_OFFSET 21 #define DARF_VMEBAR_A32BA_MASK 0x0000001F #define DARF_VMEBAR_A32SIZ_MASK 0x000001E0 #define DARF_VMEBAR_A24BA_MASK 0x001F0000 #define DARF_VMEBAR_A24SIZ_MASK 0x00600000 /* * ACC Register offsets. */ #define ACC_STAT0_OFFSET 0x00 #define ACC_STAT1_OFFSET 0x01 #define ACC_GENCTL_OFFSET 0x02 #define ACC_VINT_OFFSET 0x03 #define ACC_VREQ_OFFSET 0x04 #define ACC_VARB_OFFSET 0x05 #define ACC_ID_OFFSET 0x06 #define ACC_CTL2_OFFSET 0x07 #define ACC_7IS_OFFSET 0x08 #define ACC_LIS_OFFSET 0x09 #define ACC_7IE_OFFSET 0x0A #define ACC_LIE_OFFSET 0x0B #define ACC_VIE_OFFSET 0x0C #define ACC_IC10_OFFSET 0x0D #define ACC_IC32_OFFSET 0x0E #define ACC_IC54_OFFSET 0x0F /* * STAT0 Bit offsets and masks. */ #define ACC_STAT0_NMIP_OFFSET 0 #define ACC_STAT0_MEMF_OFFSET 1 #define ACC_STAT0_ACF_OFFSET 2 #define ACC_STAT0_SYSF_OFFSET 3 #define ACC_STAT0_VI1_OFFSET 4 #define ACC_STAT0_LTO_OFFSET 5 #define ACC_STAT0_CLRTIK_OFFSET 6 #define ACC_STAT0_CLRDOG_OFFSET 7 #define ACC_STAT0_NMIP_MASK 0x01 #define ACC_STAT0_MEMF_MASK 0x02 #define ACC_STAT0_ACF_MASK 0x04 #define ACC_STAT0_SYSF_MASK 0x08 #define ACC_STAT0_VI1_MASK 0x10 #define ACC_STAT0_LTO_MASK 0x20 #define ACC_STAT0_CLRTIK_MASK 0x40 #define ACC_STAT0_CLRDOG_MASK 0x80 /* * STAT1 Bit offsets and masks. */ #define ACC_STAT1_BGIN1_OFFSET 0 #define ACC_STAT1_BGIN2_OFFSET 1 #define ACC_STAT1_IDGOT_OFFSET 2 #define ACC_STAT1_PWRUP_OFFSET 3 #define ACC_STAT1_BIMOD_OFFSET 4 #define ACC_STAT1_SYSC_OFFSET 5 #define ACC_STAT1_BGIN1_MASK 0x01 #define ACC_STAT1_BGIN2_MASK 0x02 #define ACC_STAT1_IDGOT_MASK 0x04 #define ACC_STAT1_PWRUP_MASK 0x08 #define ACC_STAT1_BIMOD_MASK 0x10 #define ACC_STAT1_SYSC_MASK 0x20 /* * GENCTL Bit offsets and masks. */ #define ACC_GENCTL_VI1BI_OFFSET 0 #define ACC_GENCTL_IDTST_OFFSET 1 #define ACC_GENCTL_LTOEN_OFFSET 2 #define ACC_GENCTL_TLEN0_OFFSET 3 #define ACC_GENCTL_TLEN1_OFFSET 4 #define ACC_GENCTL_SBI_OFFSET 5 #define ACC_GENCTL_ABI_OFFSET 6 #define ACC_GENCTL_SWRST_OFFSET 7 #define ACC_GENCTL_VI1BI_MASK 0x01 #define ACC_GENCTL_IDTST_MASK 0x02 #define ACC_GENCTL_LTOEN_MASK 0x04 #define ACC_GENCTL_TLEN0_MASK 0x08 #define ACC_GENCTL_TLEN1_MASK 0x10 #define ACC_GENCTL_SBI_MASK 0x20 #define ACC_GENCTL_ABI_MASK 0x40 #define ACC_GENCTL_SWRST_MASK 0x80 /* Vint: VMEbus interrupt register */ #define ACC_VINT_IRQLVL_MASK 0x07 #define ACC_VINT_INT_MASK 0x08 /* Vreq: VMEbus requester register */ #define ACC_VREQ_LVL0_MASK 0x01 #define ACC_VREQ_LVL1_MASK 0x02 #define ACC_VREQ_OT0_MASK 0x04 #define ACC_VREQ_OT1_MASK 0x08 #define ACC_VREQ_REQ_MASK 0x10 #define ACC_VREQ_REL_MASK 0x20 #define ACC_VREQ_BCEN_MASK 0x40 #define ACC_VREQ_OTEN_MASK 0x80 /* Varb: VMEbus arbiter register */ #define ACC_VARB_ARB_MASK 0x03 #define ACC_VARB_ATEN_MASK 0x04 #define ACC_VARB_VXL_MASK 0x30 /* Ctl2: Control register 2 */ #define ACC_CTL2_TICKM_MASK 0x01 #define ACC_CTL2_MEMIM_MASK 0x02 #define ACC_CTL2_LBRAM_MASK 0x04 #define ACC_CTL2_BITRIG_MASK 0x10 #define ACC_CTL2_MYBBSY_MASK 0x20 /* * ACC 7IS masks and offsets. */ #define ACC_7IS_PUSH_OFFSET 0 /* NMI */ #define ACC_7IS_PARITY_OFFSET 1 /* MEM */ #define ACC_7IS_ACFAIL_OFFSET 2 /* ACF */ #define ACC_7IS_SYSFAIL_OFFSET 3 /* SYF */ #define ACC_7IS_BI_OFFSET 4 /* BI */ #define ACC_7IS_PUSH_MASK 0x01 /* NMI */ #define ACC_7IS_PARITY_MASK 0x02 /* MEM */ #define ACC_7IS_ACFAIL_MASK 0x04 /* ACF */ #define ACC_7IS_SYSFAIL_MASK 0x08 /* SYF */ #define ACC_7IS_BI_MASK 0x10 /* BI */ /* * ACC 7IE masks and offsets. */ #define ACC_7IE_PUSH_OFFSET 0 /* NMI */ #define ACC_7IE_PARITY_OFFSET 1 /* MEM */ #define ACC_7IE_ACFAIL_OFFSET 2 /* ACF */ #define ACC_7IE_SYSFAIL_OFFSET 3 /* SYF */ #define ACC_7IE_BI_OFFSET 4 /* BI */ #define ACC_7IE_PUSH_MASK 0x01 /* NMI */ #define ACC_7IE_PARITY_MASK 0x02 /* MEM */ #define ACC_7IE_ACFAIL_MASK 0x04 /* ACF */ #define ACC_7IE_SYSFAIL_MASK 0x08 /* SYF */ #define ACC_7IE_BI_MASK 0x10 /* BI */ /* * ACC IC32 Offsets and Masks */ #define ACC_IC32_2L_OFFSET 0 #define ACC_IC32_3L_OFFSET 4 #define ACC_IC32_2L_MASK 0x07 #define ACC_IC32_3L_MASK 0x70 /* * ACC IC54 Offsets and Masks */ #define ACC_IC54_4L_OFFSET 0 #define ACC_IC54_4AV_OFFSET 3 #define ACC_IC54_5L_OFFSET 4 #define ACC_IC54_5AV_OFFSET 7 #define ACC_IC54_4L_MASK 0x07 #define ACC_IC54_4AV_MASK 0x08 #define ACC_IC54_5L_MASK 0x70 #define ACC_IC54_5AV_MASK 0x80 /* * Literals used when calculating standard and extended * VMEbus addresses from the BA bits of the VMEBAR register * in the DARF. */ #define AVICS_EXTENDED_OFFSET 27 #define AVICS_STANDARD_OFFSET 3 /* * Literals used when determining if standard and extended * VMEbus addresses calculated from the BA bits of the VMEBAR register * in the DARF are legal. * The standard A24:D16 window allows for base addresses which are a * multiple of the standard BA increment defined below. * The extended A32:D32 window does not allow a Base Address ID of 0x1F. */ #define AVICS_INVALID_EXTENDED_ID 0x1F #define AVICS_STANDARD_BA_INCREMENT 0x400000 /* * Literals used to test the location monitor for all sizes * of RAM. */ #define AVICS_NUMBER_OF_STANDARD_SIZES 4 #define AVICS_NUMBER_OF_EXTENDED_SIZES 16 /*******************************/ /* Layout of the ACC registers */ /*******************************/ typedef struct acc_reg { uint8 stat0; /* ACC status register 0 */ uint8 stat1; /* ACC status register 1 */ uint8 genctl; /* General control register */ uint8 vint; /* VMEbus interrupt register */ uint8 vreq; /* VMEbus requester register */ uint8 varb; /* VMEbus arbiter register */ uint8 id; /* ID register */ uint8 ctl2; /* Control register 2 */ uint8 l7is; /* Level 7 interrupt status register */ uint8 lis; /* Local interrupt status register */ uint8 l7ie; /* Level 7 interrupt enable register */ uint8 lie; /* Local interrupt enable register */ uint8 vie; /* VMEbus interrupt enable register */ uint8 ic10; /* Local interrupts 0 & 1 control register */ uint8 ic32; /* Local interrupts 2 & 3 control register */ uint8 ic54; /* Local interrupts 4 & 5 control register */ } acc_struct; /********************************/ /* Layout of the DARF registers */ /********************************/ typedef struct darf_reg { uint32 dmasar; /* DMA source address register */ uint32 dmadar; /* DMA dest address register */ uint32 dmatc; /* DMA transfer count */ uint32 dcsr; /* DARF CSR */ uint32 vmebar; /* VMEbus base address register */ uint32 rxdat; /* RX FIFO data */ uint32 rxadd; /* RX FIFO address */ uint32 rxcnt; /* RX FIFO control bits */ uint32 vsben; /* VSB page enable register */ uint32 ivect; /* Interrupt status register */ uint32 wpbr; /* VME write-protect boundary */ uint32 dato; /* TX FIFO data output latch */ uint32 addo; /* TX FIFO address output latch */ uint32 amo; /* TX FIFO control bits output latch */ uint32 lmr; /* Location monitor msg queue */ uint32 dmode; /* DARF mode register */ uint32 sa64bar; /* Slave A64 base address register */ uint32 ma64bar; /* Master A64 base address register */ uint32 lagenr; /* Local address generator register */ uint32 dmastlr; /* DMA secondary transfer length register */ } darf_struct; /* End of file */