/*FILE HEADER************************************************************ * * File Name : $Id$ * RCS Revision Number : $Revision: 1.1 $ * Last Modified : $Date: 94/10/28 09:25:41 $ * Last Modified By : $Author: scoudray $ * CSCI Name : Version 7 Baseline Include File * Notes * This include file contains the literals used for CLIC * register accesses and bit masks. * History * Nov 11, 1991 Carolyn MacLeod * Original release * *END FILE HEADER********************************************************/ #ifdef MAKEHS #undef MAKEHS #include #endif /* * CLIC Register Offsets. */ /* Real Time Clock */ #define CLIC_RHUN_OFFSET 0x00 /* RTC hundredths of a second */ #define CLIC_RHOR_OFFSET 0x01 /* RTC hour - time of day */ #define CLIC_RMIN_OFFSET 0x02 /* RTC minutes */ #define CLIC_RSEC_OFFSET 0x03 /* RTC seconds */ #define CLIC_RMON_OFFSET 0x04 /* RTC calendar months */ #define CLIC_RDAY_OFFSET 0x05 /* RTC day of the month */ #define CLIC_RYER_OFFSET 0x06 /* RTC year */ #define CLIC_RWDY_OFFSET 0x07 /* RTC day of the week */ #define CLIC_AHUN_OFFSET 0x08 /* RTC ALARM hundredths of a second */ #define CLIC_AHOR_OFFSET 0x09 /* RTC ALARM hour */ #define CLIC_AMIN_OFFSET 0x0a /* RTC ALARM minutes */ #define CLIC_ASEC_OFFSET 0x0b /* RTC ALARM seconds */ #define CLIC_AMON_OFFSET 0x0c /* RTC ALARM calendar months */ #define CLIC_ADAY_OFFSET 0x0d /* RTC ALARM day of the month */ #define CLIC_AYER_OFFSET 0x0e /* RTC ALARM year */ #define CLIC_AWDY_OFFSET 0x0f /* RTC ALARM day of the week */ #define CLIC_RIST_OFFSET 0x10 /* RTC interrupt mask in/status out */ #define CLIC_RCSR_OFFSET 0x11 /* RTC command word */ #define CLIC_RMSK_OFFSET 0x12 /* RTC interrupt mask read */ /* Counter/Timers */ #define CLIC_TCR0_OFFSET 0x14 /* CT 8254 counter 0 value */ #define CLIC_TCR1_OFFSET 0x18 /* CT 8254 counter 1 value */ #define CLIC_TCR2_OFFSET 0x1c /* CT 8254 counter 2 value */ #define CLIC_TCRS_OFFSET 0x20 /* CT 8254 timer status/control */ #define CLIC_TCIC_OFFSET 0x24 /* CT edge triggered interrupt control */ #define CLIC_TCIS_OFFSET 0x25 /* CT interrupt status */ #define CLIC_TCCS_OFFSET 0x26 /* CT clock source control */ #define CLIC_TCCG_OFFSET 0x27 /* CT gate and clock output control */ /* Dual UARTS */ #define CLIC_UPSC_OFFSET 0x28 /* UART prescaler */ #define CLIC_UICR_OFFSET 0x29 /* UART interrupt control */ #define CLIC_ULER_OFFSET 0x2a /* UART loopback enable */ #define CLIC_UADT_OFFSET 0x2c /* UART PORT A data */ #define CLIC_UACS_OFFSET 0x30 /* UART PORT A command/status */ #define CLIC_UBDT_OFFSET 0x34 /* UART PORT B data */ #define CLIC_UBCS_OFFSET 0x38 /* UART PORT B command/status */ /* General Purpose I/O */ #define CLIC_GPDT_OFFSET 0x3c /* GPIO data read/write */ #define CLIC_GPMS_OFFSET 0x3d /* GPIO interrupt mask */ #define CLIC_GPIS_OFFSET 0x3e /* GPIO interrupt status */ #define CLIC_GPIM_OFFSET 0x3f /* GPIO immediate data read */ #define CLIC_GPDR_OFFSET 0x40 /* GPIO data direction, 0 = input */ #define CLIC_GPEG_OFFSET 0x41 /* GPIO edge compare, 0 = interrupt on */ /* RAM Control */ #define CLIC_RCVR_OFFSET 0x44 /* DRAM reset configuration */ #define CLIC_RTDC_OFFSET 0x45 /* DRAM T-bus memory control */ #define CLIC_RKDC_OFFSET 0x46 /* DRAM K-bus memory control */ #define CLIC_RPCT_OFFSET 0x48 /* DRAM parity control. NOTE: 16 bits */ #define CLIC_RTSC_OFFSET 0x4c /* DRAM parity control. NOTE: 32 bits */ #define CLIC_RKSC_OFFSET 0x50 /* DRAM parity control. NOTE: 32 bits */ #define CLIC_KLYC_OFFSET 0x54 /* DRAM parity control. NOTE: 32 bits */ /* SCSI */ #define CLIC_SRWD_OFFSET 0x58 /* SCSI current data/output data 32 bit*/ #define CLIC_SDIR_OFFSET 0x5c /* SCSI current data/output data */ #define CLIC_SICR_OFFSET 0x5d /* SCSI initiator command register */ #define CLIC_SMRR_OFFSET 0x5e /* SCSI mode register */ #define CLIC_STCR_OFFSET 0x5f /* SCSI target command register */ #define CLIC_SBSR_OFFSET 0x60 /* SCSI current bus status/select enabl*/ #define CLIC_SDMA_OFFSET 0x61 /* SCSI bus and status/start dma send */ #define CLIC_SDOR_OFFSET 0x62 /* SCSI input data/start dma target rec*/ #define CLIC_SRST_OFFSET 0x63 /* SCSI reset int/start dma initiator r*/ /* VSB/Other */ #define CLIC_VSBR_OFFSET 0x64 /* VSB configuration reg NOTE: 16 bits */ #define CLIC_PCNT_OFFSET 0x68 /* UART prescaler read reg NOTE: 16 bit*/ /* Interrupts */ #define CLIC_SAFC_OFFSET 0x74 /* Status affects vector control */ #define CLIC_GIVC_OFFSET 0x75 /* GPIO vector register */ #define CLIC_TVEC_OFFSET 0x78 /* Timer vector register */ #define CLIC_SVEC_OFFSET 0x79 /* SCSI interrupt vector */ #define CLIC_UAVC_OFFSET 0x7a /* Uart A vector register */ #define CLIC_UBVC_OFFSET 0x7b /* Uart B vector register */ #define CLIC_RTVC_OFFSET 0x7c /* RTC vector register */ #define CLIC_IPMR_OFFSET 0x7d /* CLIC peripheral vector */ #define CLIC_IPPR_OFFSET 0x7e /* CLIC interrupt priority */ #define CLIC_ACVC_OFFSET 0x7f /* Active interrupt vector */ /* * CLIC Register Contents: Bits and Masks. */ /** Real-time clock register bits **/ #define RHUN_HUNDREDTHS_MASK 0x7f #define RHOR_HRMD 0x80 #define RHOR_HOURS_MASK 0x1f #define RMIN_MINUTES_MASK 0x3f #define RSEC_SECONDS_MASK 0x3f #define RMON_MONTH_MASK 0x0f #define RDAY_DAY_MASK 0x1f #define RYER_YEAR_MASK 0x7f #define RWDY_DAY_OF_WEEK_MASK 0x07 #define AHUN_HCMP 0x80 #define AHUN_HUNDREDTHS_MASK 0x7f #define AHOR_HCMP 0x40 #define AHOR_HOURS_MASK 0x1f #define AMIN_HCMP 0x80 #define AMIN_MINUTES_MASK 0x3f #define ASEC_HCMP 0x80 #define ASEC_SECONDS_MASK 0x3f #define AMON_HCMP 0x80 #define AMON_MONTH_MASK 0x0f #define ADAY_HCMP 0x80 #define ADAY_DAY_MASK 0x1f #define AYER_HCMP 0x80 #define AYER_YEAR_MASK 0x7f #define AWDY_HCMP 0x80 #define AWDY_DAY_OF_WEEK_MASK 0x07 #define RIST_GLBL 0x80 #define RIST_DAYS 0x40 #define RIST_HOUR 0x20 #define RIST_MINS 0x10 #define RIST_SECS 0x08 #define RIST_TENS 0x04 #define RIST_HUND 0x02 #define RIST_ALARM 0x01 #define RCSR_RTEST 0x80 #define RCSR_INTEN 0x10 #define RCSR_RUN 0x08 #define RMSK_DAYS 0x40 #define RMSK_HOUR 0x20 #define RMSK_MINS 0x10 #define RMSK_SECS 0x08 #define RMSK_TENS 0x04 #define RMSK_HUND 0x02 #define RMSK_ALARM 0x01 /** Timer/counters register bits **/ #define TCIC_T2E 0x20 #define TCIC_T1E 0x10 #define TCIC_T0E 0x08 #define TCIC_T2IE 0x04 #define TCIC_T1IE 0x02 #define TCIC_T0IE 0x01 #define TCIS_T2I 0x04 #define TCIS_T1I 0x02 #define TCIS_T0I 0x01 #define TCCS_T2C1_MASK 0x30 #define TCCS_T1C1_MASK 0x0c #define TCCS_T0C1_MASK 0x03 #define TCCG_T2OE 0x08 #define TCCG_T2G 0x04 #define TCCG_T1G 0x02 #define TCCG_T0G 0x01 /** Dual UART register bits **/ /* UPSC: Uart prescaler */ #define UPSC_UPB_MASK 0x38 /* Baud rate clock for uart B */ #define UPSC_UPA_MASK 0x07 /* Baud rate clock for uart A */ /* UICR: Uart interrupt control */ #define UICR_ILIEB 0x80 /* 1 = Uart B idle line int enable */ #define UICR_RXIEB 0x40 /* 1 = Uart B receiver full int */ #define UICR_TXIEB 0x20 /* 1 = Uart B transmitter empty int */ #define UICR_TCIEB 0x10 /* 1 = Uart B tx complete int enable */ #define UICR_ILIEA 0x08 /* 1 = Uart A idle line int enable */ #define UICR_RXIEA 0x04 /* 1 = Uart A receiver full int */ #define UICR_TXIEA 0x02 /* 1 = Uart A transmitter empty int */ #define UICR_TCIEA 0x01 /* 1 = Uart A tx complete int enable */ /* ULER: Uart loopback enable */ #define ULER_CNTST 0x40 /* 1 = test mode */ #define ULER_HSKA 0x20 /* 1 = Uart A RTS in GPIO0, CTS in GPIO1 */ #define ULER_HSKB 0x10 /* 1 = Uart B RTS in GPIO2, CTS in GPIO3 */ #define ULER_UBLB 0x08 /* 1 = Enable Uart B loopback */ #define ULER_UALB 0x04 /* 1 = Enable Uart A loopback */ #define ULER_UBEN 0x02 /* 1 = Enable Uart B */ #define ULER_UAEN 0x01 /* 1 = Enable Uart A */ /* UACS: Uart port A command/status; UBCS: Uart port B command/status (same) */ /* Uart Mode/Control/Status: mode (w/o - first write after reset) */ #define UMCS_STOP_MASK 0xc0 /* Stop bits: 01 = 1, 10 = 1.5, 11 = 2 */ #define UMCS_1_STOP 0x40 /* 1 stop bit */ #define UMCS_1STOP5 0x80 /* 1.5 stop bits */ #define UMCS_2_STOP 0xc0 /* 2 stop bits */ #define UMCS_EP 0x20 /* 1 = Even parity */ #define UMCS_PEN 0x10 /* 1 = Parity enabled */ #define UMCS_L_MASK 0x0c /* Char length: 00=5 bits, 01=6, 10=7, 11=8 */ #define UMCS_5_BITS 0x00 /* 5 bit char */ #define UMCS_6_BITS 0x04 /* 6 bit char */ #define UMCS_7_BITS 0x08 /* 7 bit char */ #define UMCS_8_BITS 0x0c /* 8 bit char */ #define UMCS_B_MASK 0x03 /* Baud clock: 01=x1, 10=x16, 11=x64 */ #define UMCS_X1_CLK 0x01 /* x1 baud clock */ #define UMCS_X16_CLK 0x02 /* x16 baud clock */ #define UMCS_X64_CLK 0x03 /* x64 baud clock */ /* Uart Mode/Control/Status: control (w/o - subsequent writes after first) */ #define UMCS_RST 0x40 /* 1 = Reset internal logic */ #define UMCS_RTS 0x20 /* 1 = RTS asserted if enabled in GPIO */ #define UMCS_ERST 0x10 /* 1 = Reset error flags in status reg */ #define UMCS_BRK 0x08 /* 1 = Transmit break character */ #define UMCS_RXEN 0x04 /* 1 = Enable receiver */ #define UMCS_TXEN 0x01 /* 1 = Enable transmitter */ /* Uart Mode/Control/Status: status (r/o) */ #define UMCS_FE 0x20 /* 1 = Framing error */ #define UMCS_OE 0x10 /* 1 = Overrun error */ #define UMCS_PE 0x08 /* 1 = Parity error */ #define UMCS_TXEMP 0x04 /* 1 = Transmit FIFO full */ #define UMCS_RXRDY 0x02 /* 0 = Receiver ready */ #define UMCS_TXRDY 0x01 /* 0 = Transmitter ready */ /** General-purpose I/O register bits are card-specific. **/ /** DRAM control register bits. ** NOTE: Reset condition of bits in RCVR, RTDC, and RKDC are card-specific. **/ /* RCVR: Reset configuration vector */ #define RCVR_WIDTH 0x80 /* 0 = 32 bits, 1 = 128 bits memory bank */ #define RCVR_DRAM 0x40 /* 0 = SRAM control config, 1 = DRAM */ #define RCVR_SCSI 0x20 /* 0 = VSB enabled, 1 = SCSI enabled */ #define RCVR_PRED 0x10 /* 0 = 2 clks between RASi, 1 = 3 clocks */ #define RCVR_CBRST 0x08 /* 0 = 1 read/2 write clocks on burst, 1=2/3 */ #define RCVR_CAC_MASK 0x07 /* 0/1/2/6/7 clocks on non-burst cycle */ /* RTDC: T-bus memory control */ #define RTDC_TPRED 0x10 /* 0 = 2 clocks, 1 = 3 clocks between RASi */ #define RTDC_TDBS 0x08 /* 0 = 1r/2w, 1 = 2r/3w clocks delay on burst */ #define RTDC_TDAC_MASK 0x07 /* 0/1/2/6/7 clocks delay on 1st burst cycle */ /* RKDC: K-bus memory control */ #define RKDC_KPRED 0x10 /* 0 = 2 clocks, 1 = 3 clocks between RAS */ #define RKDC_KDBS 0x08 /* 0 = 2r/3w, 1 = 3r/4w clocks delay on burst */ #define RKDC_KDAC_MASK 0x07 /* 0/1/2/6/7 clocks delay on 1st burst cycle */ /* RPCT: Parity control. NOTE: 16 bits */ #define RPCT_PERR 0x8000 /* 1 = Parity error. NOTE: read clears */ #define RPCT_BKERR_MASK 0x3000 /* longword in error. NOTE: read clears */ #define RPCT_PER_MASK 0x0f00 /* 1 in bit = parity error in byte. Read clrs */ #define RPCT_ENINT 0x0008 /* 1 = Parity interrupt enabled */ #define RPCT_ENTEA 0x0004 /* 1 = Bus error on parity error */ #define RPCT_EVEN 0x0002 /* 1 = Set even parity */ #define RPCT_PAREN 0x0001 /* 1 = Enable parity checking */ /* RTSC: TBUS SRAM control register */ #define RTSC_KEY 0x80 #define RTSC_TSAC_MASK 0x70 #define RTSC_TSB_MASK 0x07 /* RKSC: KBUS SRAM control register */ #define RKSC_KEY 0x80 #define RKSC_KSAC_MASK 0x70 #define RKSC_KSB_MASK 0x07 /** SCSI register bits **/ #define SICR_ARST 0x80 #define SICR_A_T 0x40 #define SICR_DI_LA 0x20 #define SICR_AACK 0x10 #define SICR_ABSY 0x08 #define SICR_ASEL 0x04 #define SICR_AATN 0x02 #define SICR_ADB 0x01 #define SMRR_FRX 0x80 #define SMRR_TM 0x40 #define SMRR_EPC 0x20 #define SMRR_EPI 0x10 #define SMRR_MBSY 0x04 #define SMRR_DMA 0x02 #define SMRR_ARB 0x01 #define STCR_AREQ 0x08 #define STCR_AMSG 0x04 #define STCR_ACD 0x02 #define STCR_AIO 0x01 #define SBSR_RST 0x80 #define SBSR_BSY 0x40 #define SBSR_REQ 0x20 #define SBSR_MSG 0x10 #define SBSR_C_D 0x08 #define SBSR_I_O 0x04 #define SBSR_SEL 0x02 #define SBSR_DPB 0x01 #define SDMA_PER 0x20 #define SDMA_IRQ 0x10 #define SDMA_PHM 0x08 #define SDMA_BER 0x04 #define SDMA_ATN 0x02 #define SDMA_ACK 0x01 /** VSB and other register bits **/ #define VSBR_BTST_MASK 0x8000 #define VSBR_TBTO_MASK 0x2000 #define VSBR_LOCK_RTRY_MASK 0x1000 #define VSBR_BIMODE_MASK 0x0800 #define VSBR_CACHEN_MASK 0x0400 #define VSBR_BLOCKM_MASK 0x0200 #define VSBR_BLOCKS_MASK 0x0100 #define VSBR_SBA_MASK 0x00F8 #define VSBR_SYSCON_MASK 0x0004 #define VSBR_VSBTO_MASK 0x0002 #define VSBR_VSBEN_MASK 0x0001 /* PCNT: UART Prescaler read register */ #define PCNT_BCB 0x2000 /* baud clock for UART B */ #define PCNT_BCA 0x1000 /* baud clock for UART A */ #define PCNT_CK 0x0FFF /* baud clock timer chain taps */ /** Interrupt registers and associated bits **/ /* IPMR: CLIC peripheral vector */ #define IPMR_RTIE 0x40 /* 1 = RTCC interrupt enabled */ #define IPMR_UBIE 0x20 /* 1 = Uart B interrupt enabled */ #define IPMR_UAIE 0x10 /* 1 = Uart A interrupt enabled */ #define IPMR_SCSIE 0x08 /* 1 = SCSI interrupt enabled */ #define IPMR_CTIE 0x04 /* 1 = Timer interrupt enabled */ #define IPMR_GPIE 0x02 /* 1 = GPIO interrupt enabled */ /* IPPR: Interrupt Priority */ #define IPPR_I1P 0x02 /* 0 = timer,GPIO,SCSI 1 = SCSI,timer,GPIO */ #define IPPR_I0P 0x01 /* 0 = UARTA,UARTB,RTCC 1 = RTCC,UARTA,UARTB */ /* SAFC: Status affects vector */ #define SAFC_RTC 0x10 /* 0 = Use RTC int vec, 1 = special */ #define SAFC_UARTB 0x08 /* 0 = Use Uart B int vec, 1 = special */ #define SAFC_UARTA 0x04 /* 0 = Use Uart A int vec, 1 = special */ #define SAFC_CTC 0x02 /* 0 = Use counter/timer int vec, 1 = special */ #define SAFC_GPIO 0x01 /* 0 = Use GPIO int vec, 1 = special */ /*********************************************************************/ /* CLIC register structure - I find this easier to use than offsets. */ /*********************************************************************/ typedef struct clic_reg { volatile uint8 rhun; /* RTC hundredths of a second */ volatile uint8 rhor; /* RTC hour - time of day */ volatile uint8 rmin; /* RTC minutes */ volatile uint8 rsec; /* RTC seconds */ volatile uint8 rmon; /* RTC calendar months */ volatile uint8 rday; /* RTC day of the month */ volatile uint8 ryer; /* RTC year */ volatile uint8 rwdy; /* RTC day of the week */ volatile uint8 ahun; /* RTC ALARM hundredths of */ volatile uint8 ahor; /* RTC ALARM hour */ volatile uint8 amin; /* RTC ALARM minutes */ volatile uint8 asec; /* RTC ALARM seconds */ volatile uint8 amon; /* RTC ALARM calendar mont */ volatile uint8 aday; /* RTC ALARM day of the mo */ volatile uint8 ayer; /* RTC ALARM year */ volatile uint8 awdy; /* RTC ALARM day of the we */ volatile uint8 rist; /* RTC interrupt mask in/s */ uint8 rcsr; /* RTC command word */ volatile uint8 rmsk; /* RTC interrupt mask read */ uint8 fill1; /* Unused */ volatile uint8 tcr0; /* CT 8254 counter 0 value */ uint8 fill2[3]; /* Unused */ volatile uint8 tcr1; /* CT 8254 counter 1 value */ uint8 fill3[3]; /* Unused */ volatile uint8 tcr2; /* CT 8254 counter 2 value */ uint8 fill4[3]; /* Unused */ volatile uint8 tcrs; /* CT 8254 timer status/co */ uint8 fill5[3]; /* Unused */ uint8 tcic; /* CT edge triggered interrupt ctrl */ volatile uint8 tcis; /* CT interrupt status */ uint8 tccs; /* CT clock source control */ uint8 tccg; /* CT gate and clock outpu */ uint8 upsc; /* UART prescaler */ uint8 uicr; /* UART interrupt control */ uint8 uler; /* UART loopback enable */ uint8 fill6; /* Unused */ volatile uint8 uadt; /* UART PORT A data */ uint8 fill7[3]; /* Unused */ volatile uint8 uacs; /* UART PORT A command/sta */ uint8 fill8[3]; /* Unused */ volatile uint8 ubdt; /* UART PORT B data */ uint8 fill9[3]; /* Unused */ volatile uint8 ubcs; /* UART PORT B command/sta */ uint8 filla[3]; /* Unused */ volatile uint8 gpdt; /* GPIO data read/write */ uint8 gpms; /* GPIO interrupt mask */ volatile uint8 gpis; /* GPIO interrupt status */ volatile uint8 gpim; /* GPIO immediate data rea */ uint8 gpdr; /* GPIO data direction, 0 = input */ uint8 gpeg; /* GPIO edge compare,0 = int on rise */ uint8 fillb[2]; /* Unused */ uint8 rcvr; /* DRAM reset configuration */ uint8 rtdc; /* DRAM T-bus memory control */ uint8 rkdc; /* DRAM K-bus memory control */ uint8 fillc; /* Unused */ volatile uint16 rpct; /* DRAM parity control. NOts */ uint8 filld[2]; /* Unused */ uint32 rtsc; /* TBUS SRAM control register */ uint32 rksc; /* KBUS SRAM control register */ uint32 klyc; /* Delay line control register */ uint32 srwd; /* SCSI read/write DMA register */ volatile uint8 sdir; /* SCSI current data/outpu */ uint8 sicr; /* SCSI initiator command */ uint8 smrr; /* SCSI mode register */ volatile uint8 stcr; /* SCSI target command reg */ volatile uint8 sbsr; /* SCSI current bus statusnable */ volatile uint8 sdma; /* SCSI bus and status/stand */ uint8 sdor; /* SCSI in data/start dma target rec */ uint8 srst; /* SCSI reset int/start dma init rcv */ uint16 vsbr; /* VSB configuration register */ uint8 fille[2]; /* Unused */ volatile uint16 pcnt; /* UART prescaler read register */ uint8 fillf[10];/* Unused */ uint8 safc; /* Status affects vector control */ uint8 givc; /* GPIO vector register */ uint8 fill10[2]; /* Unused */ uint8 tvec; /* Timer vector register */ uint8 svec; /* SCSI interrupt vector */ uint8 uavc; /* Uart A vector register */ uint8 ubvc; /* Uart B vector register */ uint8 rtvc; /* RTC vector register */ uint8 ipmr; /* CLIC peripheral vector */ uint8 ippr; /* CLIC interrupt priority */ uint8 acvc; /* Active interrupt vector */ } clic_struct; /* End of file */